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公开(公告)号：USD493799S1
公开(公告)日：2004-08-03
申请号：US29195995
申请日：2003-12-18
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公开(公告)号：USD498760S1
公开(公告)日：2004-11-23
申请号：US29196558
申请日：2003-12-30
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公开(公告)号：US06963135B2
公开(公告)日：2005-11-08
申请号：US10816339
申请日：2004-03-31
IPC分类号： G11C5/04 , H01L23/31 , H01L23/538 , H01L25/065 , H01L25/10 , H01L23/34
CPC分类号： H01L23/3121 , G11C5/04 , H01L23/5388 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/45144 , H01L2224/48091 , H01L2224/49171 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package includes two substrates each having a plurality of electrical connection pads, at least one chip mounted on each of the substrates, an encapsulation body formed on each of the substrates for encapsulating the chip, and an cover for receiving the substrates and the chips therein. The chip is electrically connected to the electrical connection pads. The electrical connection pads are exposed from the cover and located on the same surface or oppositely arranged. The substrates and the cover each substantially has a rectangular shape, with a longer side of each of the substrates being vertical to a longer side of the cover. The semiconductor package is incorporated with multiple chips to enhance the performance and memory capacity thereof, and the substrates are smaller than those in the prior art and thus are more cost-effective to fabricate.
摘要翻译： 半导体封装包括两个基板，每个基板具有多个电连接焊盘，安装在每个基板上的至少一个芯片，形成在每个基板上的封装体，用于封装芯片;以及盖，用于接收基板和芯片 其中。 芯片电连接到电连接焊盘。 电连接垫从盖子露出并位于相同的表面上或相对布置。 基板和盖子基本上具有矩形形状，每个基板的较长边与盖的较长边垂直。 半导体封装结合有多个芯片以提高其性能和存储器容量，并且衬底小于现有技术中的衬底，因此制造更具成本效益。
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公开(公告)号：US20050093143A1
公开(公告)日：2005-05-05
申请号：US10816339
申请日：2004-03-31
IPC分类号： G11C5/04 , H01L23/31 , H01L23/538 , H01L25/065 , H01L25/10 , H01L23/34 , H01L23/28
CPC分类号： H01L23/3121 , G11C5/04 , H01L23/5388 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/45144 , H01L2224/48091 , H01L2224/49171 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package includes two substrates each having a plurality of electrical connection pads, at least one chip mounted on each of the substrates, an encapsulation body formed on each of the substrates for encapsulating the chip, and an cover for receiving the substrates and the chips therein. The chip is electrically connected to the electrical connection pads. The electrical connection pads are exposed from the cover and located on the same surface or oppositely arranged. The substrates and the cover each substantially has a rectangular shape, with a longer side of each of the substrates being vertical to a longer side of the cover. The semiconductor package is incorporated with multiple chips to enhance the performance and memory capacity thereof, and the substrates are smaller than those in the prior art and thus are more cost-effective to fabricate.
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公开(公告)号：US20080258306A1
公开(公告)日：2008-10-23
申请号：US12105538
申请日：2008-04-18
IPC分类号： H01L23/538 , H01L21/56
CPC分类号： H01L23/3114 , H01L21/6835 , H01L23/3135 , H01L23/3185 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/02371 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05023 , H01L2224/05026 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05684 , H01L2224/12105 , H01L2224/16145 , H01L2224/48091 , H01L2224/82001 , H01L2224/97 , H01L2225/06562 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2224/82 , H01L2924/01028 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond pads and to edges of the non-active surface; conductive traces disposed on the non-active surface of the chip; a dielectric layer covering sides of the chip and formed with a plurality of openings therein to expose a portion of the conductive traces; and a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, such that the bond pads are electrically connected to the conductive traces via the first and second metal layers.
摘要翻译： 本发明提供一种半导体器件及其制造方法。 半导体器件包括具有活性表面和相对的非活性表面的芯片，其中在有源表面上形成多个接合焊盘，并且第一金属层形成在接合焊盘和非活性表面的边缘上 ; 布置在芯片的非有源表面上的导电迹线; 介电层，其覆盖所述芯片的侧面并在其中形成有多个开口以暴露所述导电迹线的一部分; 以及多个第二金属层，形成在电介质层的开口中和第一金属层上，使得接合焊盘经由第一和第二金属层电连接到导电迹线。
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公开(公告)号：US20090057799A1
公开(公告)日：2009-03-05
申请号：US12229651
申请日：2008-08-26
CPC分类号： H01L31/0203 , H01L31/02164 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/1815 , H01L2924/00014 , H01L2924/00
摘要： A sensor semiconductor device and a method for fabricating the same are provided. At least one sensor chip is mounted and electrically connected to a lead frame. A first and a second encapsulation molding processes are sequentially performed to form a transparent encapsulant for encapsulating the sensor chip and a part of the lead frame and to form a light-impervious encapsulant for encapsulating the transparent encapsulant. The transparent encapsulant has a light-pervious portion formed at a position corresponding to and above a sensor zone of the sensor chip. The light-pervious portion is exposed from the light-impervious encapsulant. Light may penetrate the light-pervious portion, without using an additional cover board, thereby reducing manufacturing steps and costs. The above arrangement avoids prior-art problems of poor reliability caused by a porous encapsulant and poor signal reception caused by interference of ambient light entering into a conventional chip only encapsulated by a transparent encapsulant.
摘要翻译： 提供一种传感器半导体器件及其制造方法。 至少一个传感器芯片被安装并电连接到引线框架。 依次执行第一和第二封装成型工艺以形成用于封装传感器芯片和引线框架的一部分的透明密封剂，并形成用于封装透明密封剂的不透光密封剂。 透明密封剂具有形成在对应于传感器芯片的传感器区域上方的位置处的透光部分。 透光部分从不透光的密封剂暴露出来。 光可以穿透透光部分，而不使用附加的盖板，从而减少制造步骤和成本。 上述布置避免了由多孔密封剂引起的可靠性差的现有技术问题，以及由仅通过透明密封剂封装的传统芯片的环境光的干扰引起的差信号接收。
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7.发明申请Semiconductor package device, semiconductor package structure, and fabrication methods thereof 有权半导体封装器件，半导体封装结构及其制造方法公开(公告)号：US20090294959A1
公开(公告)日：2009-12-03
申请号：US12315787
申请日：2008-12-04
IPC分类号： H01L23/522 , H01L23/532 , H01L23/28 , H01L23/31
CPC分类号： H01L23/4334 , H01L21/486 , H01L23/31 , H01L23/3128 , H01L23/3135 , H01L23/49827 , H01L24/97 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/15311 , H01L2924/157 , H01L2924/3511 , H01L2924/00 , H01L2224/81
摘要： A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
摘要翻译： 提供了一种半导体封装器件，半导体封装结构及其制造方法，其主要包括在形成有TSV（透硅通孔）的晶片上设置多个半导体芯片，并将半导体芯片与TSV电连接; 用密封剂封装半导体芯片; 并将硬组分设置在密封剂上。 硬组件确保了在焊料凸块工艺期间晶片的平整度，并且在单独化处理期间提供对晶片的支撑，使得晶片可以牢固地位于单个载体上，从而克服现有技术的缺点，即难以安装焊料 碰撞，切割晶片难度大。
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公开(公告)号：US20090261476A1
公开(公告)日：2009-10-22
申请号：US12148319
申请日：2008-04-18
IPC分类号： H01L23/482 , H01L21/60
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2221/68345 , H01L2224/24226 , H01L2224/82001 , H01L2225/1035 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311
摘要： A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface.
摘要翻译： 公开了一种半导体器件及其制造方法。 该方法包括以下步骤：提供具有布置在其上的导电电路的载体板和具有设置在其上的焊料焊盘的有源表面的多个芯片，其中导电凸块设置在焊盘上; 将芯片安装在载板上; 用电介质层填充芯片之间的间隔，并在每个芯片周边的电介质层中形成开口以露出导电电路; 在所述电介质层的开口部和所述芯片的有源面的外围形成金属层，用于电连接所述导电凸块和所述导电电路; 并沿着芯片之间的电介质层切割并去除载体板以分离每个芯片并使导电电路与非活性表面相接触。
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公开(公告)号：US20090014860A1
公开(公告)日：2009-01-15
申请号：US12011832
申请日：2008-01-29
CPC分类号： H01L25/0652 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73215 , H01L2224/73265 , H01L2224/92247 , H01L2225/06562 , H01L2924/00012
摘要： A multi-chip stack structure and a manufacturing method thereof are provided. The fabrication method includes the steps of: providing a chip carrier having a first surface and a second surface opposing thereto and at least a first chip and a second chip mounted on the first surface; electrically connecting the chips to the chip carrier by a plurality of bonding wires; and stacking at least a third chip on the first and second chips by a film deposed therebetween, wherein the third chip is stepwise stacked on the first chip and at least a part of the bonding wire connected to the second chip is covered by the film, and electrically connecting the third chip and the chip carrier by a bonding wire, thereby enabling a plurality of chips to be stacked on the chip carrier to enhance the electrical performance of electronic products.
摘要翻译： 提供了一种多芯片堆叠结构及其制造方法。 该制造方法包括以下步骤：提供具有与其相对的第一表面和第二表面的芯片载体和至少安装在第一表面上的第一芯片和第二芯片; 通过多个接合线将芯片电连接到芯片载体上; 并且通过其间放置的膜将第一和第二芯片上的至少第三芯片堆叠起来，其中第三芯片逐步堆叠在第一芯片上，并且连接到第二芯片的键合线的至少一部分被膜覆盖， 并通过接合线电连接第三芯片和芯片载体，从而能够将多个芯片堆叠在芯片载体上，以增强电子产品的电气性能。
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公开(公告)号：US20060223216A1
公开(公告)日：2006-10-05
申请号：US11208269
申请日：2005-08-18
IPC分类号： H01L21/00 , H01L23/495
CPC分类号： H01L27/14618 , H01L24/97 , H01L25/167 , H01L27/14625 , H01L27/14683 , H01L2224/32225 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
摘要： A sensor module structure and a method for fabricating the same are proposed. A chip carrier module plate including a plurality of chip carriers is provided, each chip carrier having a first surface and a second surface. At least one semiconductor chip is mounted on and electrically connected to the first surface of each of the chip carriers. An encapsulation body is formed for completely encapsulating the semiconductor chips and the first surfaces of the chip carriers. A singulation process is performed to form individual package units integrated with the semiconductor chips. A sensor chip, a corresponding lens kit and a flexible printed circuit (FPC) board are attached to the second surface of each of the chip carriers, wherein the sensor chip and the FPC board are electrically connected to the chip carrier. This provides the sensor module structure fabricated with simple processes, low costs and high yields.
摘要翻译： 提出了一种传感器模块结构及其制造方法。 提供了包括多个芯片载体的芯片载体模块板，每个芯片载体具有第一表面和第二表面。 至少一个半导体芯片安装在每个芯片载体的第一表面上并电连接到每个芯片载体的第一表面。 形成用于完全封装半导体芯片和芯片载体的第一表面的封装体。 执行单个处理以形成与半导体芯片集成的单个封装单元。 传感器芯片，相应的透镜套件和柔性印刷电路板（FPC）板安装在每个芯片载体的第二表面上，其中传感器芯片和FPC基板电连接到芯片载体。 这提供了以简单的工艺制造的传感器模块结构，低成本和高产量。
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