公开(公告)号：US07577418B2

公开(公告)日：2009-08-18

申请号：US11458190

申请日：2006-07-18

Applicant: Jen-Chung Chang ,  Chia-Jung Hsu ,  Shey-Shi Lu ,  Hsiao-Chin Chen ,  Tzu-Chao Lin

Inventor： Jen-Chung Chang ,  Chia-Jung Hsu ,  Shey-Shi Lu ,  Hsiao-Chin Chen ,  Tzu-Chao Lin

IPC: H04B1/26

CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/1491 ,  H03D7/165 ,  H03D2200/0047 ,  H03D2200/009

Abstract: A sub-harmonic mixer and a down converter with the sub-harmonic mixer are provided. The sub-harmonic mixer includes a differential amplifying unit, a current buffer unit, and a switching unit. The differential amplifying unit is used to amplify a radio frequency (RF) signal and employs a first resonance circuit to force a leakage signal to flow to a first voltage. The current buffer unit is used to amplify the gain of an output signal of the differential amplifying unit and employs a second resonance circuit to force the leakage signal to flow to a second voltage. Finally, the switching unit switches an output signal of the current buffer unit into a base band signal.

Abstract translation: 提供了具有次谐波混频器的次谐波混频器和降压转换器。 子谐波混频器包括差分放大单元，当前缓冲单元和开关单元。 差分放大单元用于放大射频（RF）信号，并采用第一谐振电路来迫使泄漏信号流向第一电压。 当前的缓冲单元用于放大差分放大单元的输出信号的增益，并采用第二谐振电路来强制泄漏信号流到第二电压。 最后，切换单元将当前缓冲器单元的输出信号切换成基带信号。

公开(公告)号：US20080032659A1

公开(公告)日：2008-02-07

申请号：US11458190

申请日：2006-07-18

Applicant: Jen-Chung Chang ,  Chia-Jung Hsu ,  Shey-Shi Lu ,  Hsiao-Chin Chen ,  Tzu-Chao Lin

Inventor： Jen-Chung Chang ,  Chia-Jung Hsu ,  Shey-Shi Lu ,  Hsiao-Chin Chen ,  Tzu-Chao Lin

IPC: H04B1/18 ,  H04B1/26

CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/1491 ,  H03D7/165 ,  H03D2200/0047 ,  H03D2200/009

Abstract: A sub-harmonic mixer and a down converter with the sub-harmonic mixer are provided. The sub-harmonic mixer includes a differential amplifying unit, a current buffer unit, and a switching unit. The differential amplifying unit is used to amplify a radio frequency (RF) signal and employs a first resonance circuit to force a leakage signal to flow to a first voltage. The current buffer unit is used to amplify the gain of an output signal of the differential amplifying unit and employs a second resonance circuit to force the leakage signal to flow to a second voltage. Finally, the switching unit switches an output signal of the current buffer unit into a base band signal.

Abstract translation: 提供了具有次谐波混频器的次谐波混频器和降压转换器。 子谐波混频器包括差分放大单元，当前缓冲单元和开关单元。 差分放大单元用于放大射频（RF）信号，并采用第一谐振电路来迫使泄漏信号流向第一电压。 当前的缓冲单元用于放大差分放大单元的输出信号的增益，并采用第二谐振电路来强制泄漏信号流到第二电压。 最后，切换单元将当前缓冲器单元的输出信号切换成基带信号。

公开(公告)号：US20070296055A1

公开(公告)日：2007-12-27

申请号：US11309101

申请日：2006-06-23

Applicant: Albert Kuo Huei Yen ,  Chang-Ching Wu ,  Tzu-Chao Lin

Inventor： Albert Kuo Huei Yen ,  Chang-Ching Wu ,  Tzu-Chao Lin

IPC: H01L29/00

CPC classification number: H01L27/0251 ,  H01L23/5227 ,  H01L23/60 ,  H01L24/02 ,  H01L24/10 ,  H01L2224/0401 ,  H01L2924/14 ,  H01L2924/3011

Abstract: A radio frequency (RF) integrated circuit with electrostatic discharge (ESD) protection and an ESD protection apparatus thereof are provided. The ESD protection apparatus includes a substrate, an RF bonding pad, and an ESD protection unit. The RF bonding pad for transmitting RF signal is disposed upon the substrate. The ESD protection unit is disposed under the RF bonding pad. Wherein, The ESD protection unit includes an inductor electrically connected between the RF bonding pad and the power rail.

Abstract translation: 提供一种具有静电放电（ESD）保护的射频（RF）集成电路及其ESD保护装置。 ESD保护装置包括衬底，RF焊盘和ESD保护单元。 用于发送RF信号的RF焊盘设置在基板上。 ESD保护单元设置在RF焊盘下方。 其中，ESD保护单元包括电连接在RF焊盘和电源轨之间的电感器。

公开(公告)号：US07199742B2

公开(公告)日：2007-04-03

申请号：US11161302

申请日：2005-07-29

Applicant: Tzu-Chao Lin ,  Yuan-Hui Chen ,  Hai-Thanh Nguyen

Inventor： Tzu-Chao Lin ,  Yuan-Hui Chen ,  Hai-Thanh Nguyen

IPC: H03M1/66

CPC classification number: H03K3/35613 ,  H03M1/0617 ,  H03M1/685

Abstract: A digital-to-analog converter has a plurality of current cells. Each of the current cells has a level shifter and a current source. The level shifter connects to a first power terminal and a second power terminal to convert a first input signal and a second input signal into a first output signal and a second output signal. The current source has two cascaded MOS transistors connected to the first power terminal in series, a first MOS switch having a gate for receiving the first output signal, and a second MOS switch having a gate for receiving the second output signal. A voltage level of the first power terminal is greater than a voltage level of the second power terminal. When one of the current cells operates, one of the first MOS switch and the second MOS switch of the current source is turned on and operates in a saturation region.

Abstract translation: 数模转换器具有多个当前单元。 每个当前单元都具有电平移位器和电流源。 电平移位器连接到第一电源端子和第二电源端子，以将第一输入信号和第二输入信号转换为第一输出信号和第二输出信号。 电流源具有串联连接到第一电源端子的两个级联MOS晶体管，具有用于接收第一输出信号的栅极的第一MOS开关和具有用于接收第二输出信号的栅极的第二MOS开关。 第一电源端子的电压电平大于第二电源端子的电压电平。 当当前单元之一工作时，电流源的第一MOS开关和第二MOS开关中的一个导通，并在饱和区域中工作。

公开(公告)号：US07636018B2

公开(公告)日：2009-12-22

申请号：US11686092

申请日：2007-03-14

Applicant: Jen-Chung Chang ,  Chia-Jung Hsu ,  Shey-Shi Lu ,  Yu-Che Yang ,  Tsung-Chien Wu ,  Tzu-Chao Lin

Inventor： Jen-Chung Chang ,  Chia-Jung Hsu ,  Shey-Shi Lu ,  Yu-Che Yang ,  Tsung-Chien Wu ,  Tzu-Chao Lin

IPC: H03L7/00

CPC classification number: H03L7/1976 ,  H03L7/081 ,  H03L7/087

Abstract: In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

Abstract translation: 在锁相环（PLL）中，移相器移位输入信号的相位。 基于输入信号的相位，移位的信号和分频输出信号，相位频率检测器（PFD）产生相位差信号。 响应于相位差信号，电荷泵（CP）控制其输出电压。 基于CP的输出电压，压控振荡器（VCO）输出输出信号。 分频器分频来自VCO的输出信号的频率，以产生分频输出信号。 循环器在正确的时机将分频输出信号输出到一个PFD。 调制器减少了分频器的量化误差。

公开(公告)号：US20070024479A1

公开(公告)日：2007-02-01

申请号：US11161302

申请日：2005-07-29

Applicant: Tzu-Chao Lin ,  Yuan-Hui Chen ,  Hai-Thanh Nguyen

Inventor： Tzu-Chao Lin ,  Yuan-Hui Chen ,  Hai-Thanh Nguyen

IPC: H03M1/66

CPC classification number: H03K3/35613 ,  H03M1/0617 ,  H03M1/685

Abstract: A digital-to-analog converter has a plurality of current cells. Each of the current cells has a level shifter and a current source. The level shifter connects to a first power terminal and a second power terminal to convert a first input signal and a second input signal into a first output signal and a second output signal. The current source has two cascaded MOS transistors connected to the first power terminal in series, a first MOS switch having a gate for receiving the first output signal, and a second MOS switch having a gate for receiving the second output signal. A voltage level of the first power terminal is greater than a voltage level of the second power terminal. When one of the current cells operates, one of the first MOS stitch and the second MOS switch of the current source is turned on and operates in a saturation region.

Abstract translation: 数模转换器具有多个当前单元。 每个当前单元都具有电平移位器和电流源。 电平移位器连接到第一电源端子和第二电源端子，以将第一输入信号和第二输入信号转换为第一输出信号和第二输出信号。 电流源具有串联连接到第一电源端子的两个级联MOS晶体管，具有用于接收第一输出信号的栅极的第一MOS开关和具有用于接收第二输出信号的栅极的第二MOS开关。 第一电源端子的电压电平大于第二电源端子的电压电平。 当当前单元之一工作时，电流源的第一MOS线圈和第二MOS开关中的一个导通，并在饱和区域中工作。

公开(公告)号：US20080224789A1

公开(公告)日：2008-09-18

申请号：US11686092

申请日：2007-03-14

Applicant: Jen-Chung Chang ,  Chia-Jung Hsu ,  Shey-Shi Lu ,  Yu-Che Yang ,  Tsung-Chien Wu ,  Tzu-Chao Lin

Inventor： Jen-Chung Chang ,  Chia-Jung Hsu ,  Shey-Shi Lu ,  Yu-Che Yang ,  Tsung-Chien Wu ,  Tzu-Chao Lin

IPC: H03C3/06 ,  H03L7/00

CPC classification number: H03L7/1976 ,  H03L7/081 ,  H03L7/087

Abstract: In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

Abstract translation: 在锁相环（PLL）中，移相器移位输入信号的相位。 基于输入信号的相位，移位的信号和分频输出信号，相位频率检测器（PFD）产生相位差信号。 响应于相位差信号，电荷泵（CP）控制其输出电压。 基于CP的输出电压，压控振荡器（VCO）输出输出信号。 分频器分频来自VCO的输出信号的频率，以产生分频输出信号。 循环器在正确的时机将分频输出信号输出到一个PFD。 调制器减少了分频器的量化误差。