-
公开(公告)号：US20130191061A1
公开(公告)日：2013-07-25
申请号：US13610842
申请日：2012-09-11
IPC分类号： G06F19/00
CPC分类号： G04F10/005
摘要： A method of estimating gain of a time-to-digital converter (TDC) includes: capturing a TDC output sample; calculating a gradient in response to the TDC output sample; and adjusting a TDC normalizing gain based on the calculating step. Another method of calibrating gain of a TDC includes: capturing a phase error which is derived from a TDC output sample, a reference phase and a variable phase; calculating a gradient in response to the phase error; and adjusting a TDC normalizing gain based on the calculating step.
摘要翻译： 一种估计时间 - 数字转换器（TDC）的增益的方法包括：捕获TDC输出样本; 计算响应于TDC输出样本的梯度; 以及基于所述计算步骤调整TDC归一化增益。 校准TDC增益的另一种方法包括：捕获从TDC输出样本，参考相位和可变相位导出的相位误差; 计算响应于相位误差的梯度; 以及基于所述计算步骤调整TDC归一化增益。
-
公开(公告)号：US20130187800A1
公开(公告)日：2013-07-25
申请号：US13610827
申请日：2012-09-11
IPC分类号： H03M1/12
CPC分类号： G04F10/005
摘要： A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.
摘要翻译： 一种估计时间 - 数字转换器（TDC）的不匹配的方法包括：捕获相位误差样本; 计算相位误差样本与相位误差样本的期望值之间的差异; 以及基于所述计算步骤调整所述TDC的校正增益。 估计TDC不匹配的另一种方法包括：捕获TDC输出码样本; 分别存储对应于不同TDC值的多个累加值，其中每个累积值记录TDC输出代码样本携带TDC值的次数; 基于累积值计算期望值; 计算积累值和期望值之间的差异; 以及基于所述计算步骤调整所述TDC的校正增益。
-
公开(公告)号：US09207646B2
公开(公告)日：2015-12-08
申请号：US13610842
申请日：2012-09-11
CPC分类号： G04F10/005
摘要： A method of estimating gain of a time-to-digital converter (TDC) includes: capturing a TDC output sample; calculating a gradient in response to the TDC output sample; and adjusting a TDC normalizing gain based on the calculating step. Another method of calibrating gain of a TDC includes: capturing a phase error which is derived from a TDC output sample, a reference phase and a variable phase; calculating a gradient in response to the phase error; and adjusting a TDC normalizing gain based on the calculating step.
摘要翻译： 一种估计时间 - 数字转换器（TDC）的增益的方法包括：捕获TDC输出样本; 计算响应于TDC输出样本的梯度; 以及基于所述计算步骤调整TDC归一化增益。 校准TDC增益的另一种方法包括：捕获从TDC输出样本，参考相位和可变相位导出的相位误差; 计算响应于相位误差的梯度; 以及基于所述计算步骤调整TDC归一化增益。
-
公开(公告)号：US08669890B2
公开(公告)日：2014-03-11
申请号：US13610827
申请日：2012-09-11
IPC分类号： H03M1/06
CPC分类号： G04F10/005
摘要： A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.
摘要翻译： 一种估计时间 - 数字转换器（TDC）的不匹配的方法包括：捕获相位误差样本; 计算相位误差样本与相位误差样本的期望值之间的差异; 以及基于所述计算步骤调整所述TDC的校正增益。 估计TDC不匹配的另一种方法包括：捕获TDC输出码样本; 分别存储对应于不同TDC值的多个累加值，其中每个累积值记录TDC输出代码样本携带TDC值的次数; 基于累积值计算期望值; 计算积累值和期望值之间的差异; 以及基于所述计算步骤调整所述TDC的校正增益。
-
5.发明申请POLAR TRANSMITTER HAVING FREQUENCY MODULATING PATH WITH INTERPOLATION IN COMPENSATING FEED INPUT AND RELATED METHOD THEREOF 有权具有补偿进给输入的插补的频率调制路径的极性发射器及其相关方法公开(公告)号：US20130187688A1
公开(公告)日：2013-07-25
申请号：US13612770
申请日：2012-09-12
IPC分类号： H03L7/08
CPC分类号： H03C5/00 , H04L7/002 , H04L7/0331
摘要： A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.
摘要翻译： 用于产生频率调制时钟的频率调制路径包括直接调制振荡器频率的直接馈送输入和用于补偿频率调制对相位误差的影响的补偿馈入输入; 其中所述补偿馈送输入由作为所述振荡器的整数边缘除法的下分频时钟再采样。 用于产生参考相位输出的参考相位发生器包括重采样电路，累加器和采样器。 重采样电路用于对调制频率指令字（FCW）进行重采样以产生多个采样。 累加器用于累积样本以产生累积结果。 采样器用于根据频率参考时钟对累积结果进行采样，并且因此产生采样结果，其中至少根据采样结果来更新参考相位输出。
-
6.发明授权Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof 有权时钟发生器，用于产生与输入时钟非谐波关系的输出时钟及其相关的时钟产生方法公开(公告)号：US08493107B2
公开(公告)日：2013-07-23
申请号：US13170197
申请日：2011-06-28
IPC分类号： H03L7/00
CPC分类号： H03K5/131 , H03L7/0996
摘要： One clock generator includes an oscillator block, a delay circuit, and an output block. The oscillator block provides a first clock of multiple phases. The delay circuit delays at least one of said multiple phases of said first clock to generate a second clock of multiple phases. The output block generates a third clock by selecting signals from said multiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. Another exemplary clock generator includes an oscillator block and an output block. The oscillator block includes an oscillator arranged to provide a first clock, and a delay locked loop arranged to generate a second clock according to said first clock. The output block generates a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock.
摘要翻译： 一个时钟发生器包括一个振荡器模块，一个延迟电路和一个输出模块。 振荡器模块提供多个阶段的第一个时钟。 所述延迟电路延迟所述第一时钟的所述多个相位中的至少一个以产生多相的第二时钟。 输出块通过从所述第二时钟的所述多个相位选择信号来产生第三时钟，其中所述第三时钟与所述第一时钟具有非谐波关系。 另一示例性时钟发生器包括振荡器模块和输出模块。 振荡器模块包括布置成提供第一时钟的振荡器和布置成根据所述第一时钟产生第二时钟的延迟锁定环。 输出块通过从所述多个相位选择信号来产生第三时钟，其中所述第三时钟与所述第一时钟具有非谐波关系。
-
7.发明授权Polar transmitter having frequency modulating path with interpolation in compensating feed input and related method thereof 有权具有补偿馈入输入插值的频率调制路径的极性发射机及其相关方法公开(公告)号：US08947172B2
公开(公告)日：2015-02-03
申请号：US13612770
申请日：2012-09-12
CPC分类号： H03C5/00 , H04L7/002 , H04L7/0331
摘要： A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.
摘要翻译： 用于产生频率调制时钟的频率调制路径包括直接调制振荡器频率的直接馈送输入和用于补偿频率调制对相位误差的影响的补偿馈入输入; 其中所述补偿馈送输入由作为所述振荡器的整数边缘除法的下分频时钟再采样。 用于产生参考相位输出的参考相位发生器包括重采样电路，累加器和采样器。 重采样电路用于对调制频率指令字（FCW）进行重采样以产生多个采样。 累加器用于累积样本以产生累积结果。 采样器用于根据频率参考时钟对累积结果进行采样，并且因此产生采样结果，其中至少根据采样结果来更新参考相位输出。
-
8.发明授权Apparatus and method for calibrating timing mismatch of edge rotator operating on multiple phases of oscillator 有权用于校准在振荡器的多个相位上操作的边沿旋转器的定时失配的装置和方法公开(公告)号：US08816780B2
公开(公告)日：2014-08-26
申请号：US13170187
申请日：2011-06-28
CPC分类号： H03L7/0996
摘要： An exemplary calibration apparatus for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes a capturing block arranged to capture phase error samples, and a calibrating block arranged to adjust timing of said edge rotator according to said phase error samples. An exemplary calibration method for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes the following steps: capturing phase error samples, and adjusting timing of said edge rotator according to said phase error samples.
摘要翻译： 用于校准在振荡器的多相上操作的边缘旋转器的定时失配的示例性校准装置包括布置成捕获相位误差采样的捕获块，以及被配置为根据所述相位误差样本调整所述边缘旋转器的定时的校准块。 用于校准在振荡器的多相上操作的边缘旋转器的定时失配的示例性校准方法包括以下步骤：捕获相位误差样本，并根据所述相位误差样本调整所述边缘旋转器的定时。
-
9.发明授权公开(公告)号：US08804874B2
公开(公告)日：2014-08-12
申请号：US13612796
申请日：2012-09-12
IPC分类号： H03C3/00
CPC分类号： H03C5/00 , H04L7/002 , H04L7/0331
摘要： A polar transmitter includes a frequency modulating path, a clock divider and a digital processing block. The frequency modulating path is arranged for generating a frequency modulated clock in response to a frequency modulating signal. The clock divider is coupled to the frequency modulated clock, and arranged for generating a down-divided clock. The digital processing block is coupled to the down-divided clock, and arranged for generating the frequency modulating signal, wherein the frequency modulating signal is adjusted for frequency deviation of the frequency modulated clock. A method for polar transmission includes: generating a frequency modulated clock in response to a frequency modulating signal; dividing a frequency of said frequency modulated clock to generate a down-divided clock; and generating said frequency modulating signal according to said down-divided clock, wherein said frequency modulating signal is adjusted for frequency deviation of said frequency modulated clock.
摘要翻译： 极性发射机包括频率调制路径，时钟分频器和数字处理模块。 频率调制路径被布置成响应于频率调制信号而产生调频时钟。 时钟分频器耦合到频率调制时钟，并且被布置用于产生分频时钟。 数字处理块耦合到分频时钟，并且被配置为产生频率调制信号，其中调频信号针对频率调制时钟的频率偏差。 一种用于极性传输的方法包括：响应于频率调制信号产生调频时钟; 将所述调频时钟的频率除以产生下降时钟; 以及根据所述分频时钟产生所述频率调制信号，其中调节所述频率调制信号以调节所述频率调制时钟的频率偏差。
-
10.发明授权Frequency modulator having digitally-controlled oscillator with modulation tuning and phase-locked loop tuning 有权具有调制调谐和锁相环调谐的数字控制振荡器的频率调制器公开(公告)号：US08952763B2
公开(公告)日：2015-02-10
申请号：US13612767
申请日：2012-09-12
CPC分类号： H03C3/0958 , H04L27/12 , H04L27/127
摘要： A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.
摘要翻译： 频率调制器包括数字控制振荡器（DCO），其被配置为响应于调制调谐字和锁相环（PLL）调谐字产生频率偏差。 此外，另一个频率调制器包括DCO和DCO接口电路。 DCO被布置成响应于整数调整字和分数调谐字产生频率偏差。 DCO接口电路用于将整数调整字和分数调谐字产生到DCO，其中分数调谐字通过定点调谐字的异步采样获得。
-
-
-
-
-
-
-
-
-
搜索结果
24 条记录 (耗时 0.019 秒)
