公开(公告)号：US08547267B2

公开(公告)日：2013-10-01

申请号：US13481990

申请日：2012-05-29

申请人： Alan Roth ,  Eric Soenen ,  Chia Liang Tai

发明人： Alan Roth ,  Eric Soenen ,  Chia Liang Tai

IPC分类号： H03M3/00

CPC分类号： G05B11/01 ,  G01K7/16 ,  G01K15/005 ,  G05B15/02 ,  H03M3/344 ,  H03M3/458

摘要： A hysteretic digital filter includes a first multi-bit flip-flop having an input for receiving a series of multi-bit sigma-delta ADC codes, a clock input for receiving a clock signal and an output; a second multi-bit flip-flop having an input coupled to the output of the first multi-bit flip-flop, an output for providing an output code of the digital filter, and an input for receiving a latch control signal, the second multi-bit flip-flop latching its input to its output under control of the latch control signal; and a control circuit. The control circuit is configured to selectively provide the latch control signal to trigger latching by the second multi-bit flip-flop dependent on a running comparison of the output code of the digital filter and the value of individual ones of the multi-bit sigma-delta ADC codes from the series of multi-bit sigma-delta ADC codes.

摘要翻译： 迟滞数字滤波器包括具有用于接收一系列多比特Σ-ΔADC码的输入的第一多位触发器，用于接收时钟信号和输出的时钟输入; 具有耦合到第一多位触发器的输出的输入的第二多位触发器，用于提供数字滤波器的输出码的输出和用于接收锁存控制信号的输入，第二多位触发器 位触发器在锁存控制信号的控制下将其输入锁存到其输出端; 和控制电路。 控制电路被配置为根据数字滤波器的输出代码的运行比较和多比特Σ-位触发器的各个值的选择性地提供锁存控制信号以触发第二多位触发器的锁存， 来自多位Σ-ΔADC代码的Delta ADC代码。

公开(公告)号：US09143033B2

公开(公告)日：2015-09-22

申请号：US12956630

申请日：2010-11-30

申请人： Chia-Liang Tai ,  Alan Roth ,  Eric Soenen

发明人： Chia-Liang Tai ,  Alan Roth ,  Eric Soenen

IPC分类号： G05F1/00 ,  H02M3/156 ,  G05F1/40 ,  G05F1/10

CPC分类号： G05F1/575 ,  G01R1/203 ,  G05F1/00 ,  G05F1/10 ,  G05F1/40 ,  G05F1/56 ,  H02M3/156

摘要： A hysteretic power converter includes a comparator, a calibration circuit, and an output node having an output voltage. The calibration circuit is configured to supply a calibrated voltage to the comparator. The comparator controls the output voltage based on the calibrated voltage and a feedback voltage representing at least a portion of the output voltage.

摘要翻译： 迟滞功率转换器包括比较器，校准电路和具有输出电压的输出节点。 校准电路被配置为向比较器提供经校准的电压。 比较器基于校准的电压和表示输出电压的至少一部分的反馈电压来控制输出电压。

公开(公告)号：US20090237966A1

公开(公告)日：2009-09-24

申请号：US12197790

申请日：2008-08-25

申请人： Eric Soenen ,  Alan Roth ,  Martin Kinyua ,  Justin Shi

发明人： Eric Soenen ,  Alan Roth ,  Martin Kinyua ,  Justin Shi

IPC分类号： H02M3/00

CPC分类号： H02M3/1588 ,  H02M2001/0012 ,  Y02B70/1466

摘要： A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal.

摘要翻译： 提出了一种用于控制功率转换器的系统和方法。 实施例包括连接到模拟 - 数字转换器的模拟差分电路，并将数字误差信号与至少第一阈值进行比较。 如果数字误差信号小于第一阈值，则产生脉冲以控制功率转换器。 另一实施例包括可与数字误差信号进行比较的多个阈值。

公开(公告)号：US20090237959A1

公开(公告)日：2009-09-24

申请号：US12134930

申请日：2008-06-06

申请人： Eric Soenen ,  Alan Roth ,  Justin Shi ,  Martin Kinyua

发明人： Eric Soenen ,  Alan Roth ,  Justin Shi ,  Martin Kinyua

IPC分类号： H02M7/00

CPC分类号： H02M3/1588 ,  H02M2001/0012 ,  Y02B70/1466

摘要： A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, a digital pulse generator, and a pre-driver to control the power converter. Another embodiment also includes a digital filter as part of the control loop that may be used to control the loop characteristics of the control circuit. Yet another embodiment replaces the differential circuit with a sigma-delta analog-to-digital modulator and a decimator.

摘要翻译： 提出了一种用于控制功率转换器的系统和方法。 实施例包括连接到模拟 - 数字转换器的模拟差分电路，数字脉冲发生器和用于控制功率转换器的预驱动器。 另一实施例还包括作为可用于控制控制电路的环路特性的控制环路的一部分的数字滤波器。 另一个实施例用Σ-Δ模数转换器和抽取器代替了差分电路。

公开(公告)号：US09479051B2

公开(公告)日：2016-10-25

申请号：US13340746

申请日：2011-12-30

申请人： Chien-Chung Tseng ,  Eric Soenen ,  Alan Roth ,  Justin Shi

发明人： Chien-Chung Tseng ,  Eric Soenen ,  Alan Roth ,  Justin Shi

IPC分类号： G05F1/577 ,  H02M3/158 ,  H02M1/00

CPC分类号： H02M3/158 ,  H02M2001/009

摘要： A DC to DC converter includes a switching circuit and a controller. The switching circuit includes an inductor coupled to first and second voltage supply nodes and to a plurality of output loads. The controller is configured to monitor a current through the inductor and to selectively couple the inductor to each of the plurality of output loads such that at least one of the following criteria is met: 1) an average current through the inductor is minimized for the particular output loads coupled to the switching circuit, or 2) minimize a number of times the switching circuit is switched during a charging period for the particular output loads coupled to the switching circuit.

摘要翻译： DC-DC转换器包括开关电路和控制器。 开关电路包括耦合到第一和第二电压供应节点和耦合到多个输出负载的电感器。 控制器被配置为监测通过电感器的电流并且选择性地将电感器耦合到多个输出负载中的每一个，使得满足以下标准中的至少一个：1）通过电感器的平均电流对于特定的 耦合到开关电路的输出负载，或2）在耦合到开关电路的特定输出负载的充电周期期间最小化开关电路切换的次数。

公开(公告)号：US08971004B2

公开(公告)日：2015-03-03

申请号：US13546303

申请日：2012-07-11

申请人： Alan Roth ,  Eric Soenen

发明人： Alan Roth ,  Eric Soenen

IPC分类号： H02H5/04

CPC分类号： G05B11/01 ,  G01K7/16 ,  G01K15/005 ,  G05B15/02 ,  H03M3/344 ,  H03M3/458

摘要： A high accuracy on-chip thermal sensor includes an integrated circuit and sensing elements. The thermal sensor finds application in various mobile and battery powered devices and includes a processor that analyzes a measured temperature signal and decides if the thermal sensor operates in low or high power operational mode, or if the device's CPU is to be reset. A method utilizing the thermal sensor includes making comparisons to two threshold temperatures and operating at low power mode below the first threshold temperature, high power mode between the two threshold temperatures and causing reset if the second threshold temperature is exceeded. Low power operational mode includes a lower clock frequency, lower bias current and lower power consumption. Higher power operational mode is used when the upper threshold temperature is being approached and includes a higher data sampling frequency and more accurate temperature control and uses higher power.

摘要翻译： 高精度片上热传感器包括集成电路和感测元件。 热传感器可用于各种移动和电池供电的设备，并包括一个处理器，用于分析测量的温度信号，并决定热传感器是在低功耗还是高功率运行模式下运行，或者设备的CPU是否被复位。 利用热传感器的方法包括比较两个阈值温度并在低于第一阈值温度的低功率模式下工作，在两个阈值温度之间的高功率模式，并且如果超过第二阈值温度则引起复位。 低功耗操作模式包括较低的时钟频率，较低的偏置电流和较低的功耗。 当接近上限阈值时使用更高功率的工作模式，并且包括更高的数据采样频率和更准确的温度控制，并且使用更高的功率。

公开(公告)号：US08324955B2

公开(公告)日：2012-12-04

申请号：US13051343

申请日：2011-03-18

申请人： Alan Roth ,  Ying-Chih Hsu ,  Justin Shi ,  Eric Soenen

发明人： Alan Roth ,  Ying-Chih Hsu ,  Justin Shi ,  Eric Soenen

IPC分类号： H03L5/00

CPC分类号： H03K19/018507 ,  H03K3/037

摘要： A level shifter receives an input voltage signal and produces an output voltage signal. The level shifter includes a first inverter, configured to operate at a potential difference between a first voltage V1 and a second voltage V2. The output from the invert is capacitively coupled to an input of a latch circuit via a capacitor. The capacitor has a first terminal connected to the output terminal of the first inverter, and further has a second terminal. The level shifter has a resistor connected to a third voltage V3 and to the capacitor for tying the input to the latch circuit to a desired voltage. The latch circuit is configured to operate at a potential difference between a fourth voltage V4 and a fifth voltage V5. The latch has an input node connected to the resistor and the capacitor, and further has an output node connected to an output node of the level shifter.

摘要翻译： 电平移位器接收输入电压信号并产生输出电压信号。 电平移位器包括第一反相器，其被配置为在第一电压V1和第二电压V2之间的电位差下工作。 反相器的输出通过电容电容耦合到锁存电路的输入端。 电容器具有连接到第一反相器的输出端子的第一端子，并且还具有第二端子。 电平移位器具有连接到第三电压V3的电阻器和用于将输入端连接到锁存电路的电容器以达到期望的电压。 闩锁电路被配置为在第四电压V4和第五电压V5之间的电位差下工作。 锁存器具有连接到电阻器和电容器的输入节点，并且还具有连接到电平移位器的输出节点的输出节点。

公开(公告)号：US20130082668A1

公开(公告)日：2013-04-04

申请号：US13340746

申请日：2011-12-30

申请人： Chien-Chung Tseng ,  Eric Soenen ,  Alan Roth ,  Justin Shi

发明人： Chien-Chung Tseng ,  Eric Soenen ,  Alan Roth ,  Justin Shi

IPC分类号： G05F1/577

CPC分类号： H02M3/158 ,  H02M2001/009

摘要： A DC to DC converter includes a switching circuit and a controller. The switching circuit includes an inductor coupled to first and second voltage supply nodes and to a plurality of output loads. The controller is configured to monitor a current through the inductor and to selectively couple the inductor to each of the plurality of output loads such that at least one of the following criteria is met: 1) an average current through the inductor is minimized for the particular output loads coupled to the switching circuit, or 2) minimize a number of times the switching circuit is switched during a charging period for the particular output loads coupled to the switching circuit.

摘要翻译： DC-DC转换器包括开关电路和控制器。 开关电路包括耦合到第一和第二电压供应节点和耦合到多个输出负载的电感器。 控制器被配置为监测通过电感器的电流并且选择性地将电感器耦合到多个输出负载中的每一个，使得满足以下标准中的至少一个：1）通过电感器的平均电流对于特定的 耦合到开关电路的输出负载，或2）在耦合到开关电路的特定输出负载的充电周期期间最小化开关电路切换的次数。

公开(公告)号：US20110089916A1

公开(公告)日：2011-04-21

申请号：US12857092

申请日：2010-08-16

申请人： Eric Soenen ,  Alan Roth ,  Justin Shi ,  Ying-Chih Hsu ,  Guang-Cheng Wang ,  Wen-Shen Chou

发明人： Eric Soenen ,  Alan Roth ,  Justin Shi ,  Ying-Chih Hsu ,  Guang-Cheng Wang ,  Wen-Shen Chou

IPC分类号： G05F1/10

CPC分类号： G05F1/575 ,  H02M3/07 ,  H02M2001/0045

摘要： Embodiments of the invention are related to LDO regulators. In an embodiment, an amplifier drives the gate of a master source follower and of at least one slave source follower to form an LDO regulator. In an alternative embodiment, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance. Other embodiments are also disclosed.

摘要翻译： 本发明的实施例涉及LDO调节器。 在一个实施例中，放大器驱动主源跟随器的栅极和至少一个从源极跟随器的栅极以形成LDO调节器。 在替代实施例中，电荷泵驱动主源极跟随器以形成调节器。 附加的从源跟随器可以与电荷泵和主源极跟随器一起使用，以改善调节器的性能。 还公开了其他实施例。

公开(公告)号：US20110006844A1

公开(公告)日：2011-01-13

申请号：US12858310

申请日：2010-08-17

申请人： Eric Soenen ,  Alan Roth ,  Justin Shi ,  Martin Kinyua

发明人： Eric Soenen ,  Alan Roth ,  Justin Shi ,  Martin Kinyua

IPC分类号： H03F3/217

CPC分类号： H03F3/2173

摘要： Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier.

摘要翻译： D类放大器的电路和方法。 在一个示例性实施例中，公开了一种音频放大器。 提供用于驱动高侧和低侧驱动晶体管的闭环配置，每个电路与先进的亚微米半导体工艺兼容。 模拟时变输入耦合到Σ-Δ模数转换器的一个输入端。 来自输出的反馈信号也被输入到模数转换器。 位流由模数转换器输出。 抽取器接收该位流，并以较低的频率将样本下变频为数字值。 使用具有适应系数的数字滤波器来对该信号进行滤波，并且数字脉宽调制器然后开发模拟差分PWM信号。 预驱动器输入PWM信号并导出输出门控信号以控制D类放大器的高侧和低侧驱动器。