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    MOSFET device with localized stressor
    2.
    发明授权
    MOSFET device with localized stressor 有权
    具有局部应力源的MOSFET器件

    公开(公告)号：US08557669B2

    公开(公告)日：2013-10-15

    申请号：US12176655

    申请日：2008-07-21

    申请人： Chien-Hao Chen ,  Pang-Yen Tsai ,  Chie-Chien Chang ,  Tze-Liang Lee ,  Shih-Chang Chen

    发明人： Chien-Hao Chen ,  Pang-Yen Tsai ,  Chie-Chien Chang ,  Tze-Liang Lee ,  Shih-Chang Chen

    IPC分类号： H01L21/42

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/45 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.

    摘要翻译： 提供具有局部应力的MOSFET。 MOSFET具有形成在源极/漏极区域中的应力诱导层，其中应力诱导层包括第一半导体材料和第二半导体材料。 对应力诱导层进行处理，使得由第一半导体材料引起反应，并且第二半导体材料被迫下降到应力诱导层中。 应力诱导层可以是凹陷区域或非凹陷区域。 第一种方法包括在源极/漏极区域中形成诸如SiGe的应力诱导层并进行氮化或氧化过程。 在应力诱导层的顶部形成氮化物或氧化物膜，迫使Ge较低进入应力诱导层。 另一方法实施例涉及在应力诱导层上形成反应层，并进行处理工艺以使反应层与应力诱导层反应。

    MOSFET Device With Localized Stressor
    3.
    发明申请
    MOSFET Device With Localized Stressor 有权
    具有局部应力的MOSFET器件

    公开(公告)号：US20100015814A1

    公开(公告)日：2010-01-21

    申请号：US12176655

    申请日：2008-07-21

    申请人： Chien-Hao Chen ,  Pang-Yen Tsai ,  Chie-Chien Chang ,  Tze-Liang Lee ,  Shih-Chang Chen

    发明人： Chien-Hao Chen ,  Pang-Yen Tsai ,  Chie-Chien Chang ,  Tze-Liang Lee ,  Shih-Chang Chen

    IPC分类号： H01L21/31

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/45 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.

    摘要翻译： 提供具有局部应力的MOSFET。 MOSFET具有形成在源极/漏极区域中的应力诱导层，其中应力诱导层包括第一半导体材料和第二半导体材料。 对应力诱导层进行处理，使得由第一半导体材料引起反应，并且第二半导体材料被迫下降到应力诱导层中。 应力诱导层可以是凹陷区域或非凹陷区域。 第一种方法包括在源极/漏极区域中形成诸如SiGe的应力诱导层并进行氮化或氧化过程。 在应力诱导层的顶部形成氮化物或氧化物膜，迫使Ge较低进入应力诱导层。 另一方法实施例涉及在应力诱导层上形成反应层，并进行处理工艺以使反应层与应力诱导层反应。

    Super anneal for process induced strain modulation
    6.
    发明授权
    Super anneal for process induced strain modulation 有权
    过程诱导应变调制的超退火

    公开(公告)号：US07528028B2

    公开(公告)日：2009-05-05

    申请号：US11199011

    申请日：2005-08-08

    申请人： Mong Song Liang ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

    发明人： Mong Song Liang ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823412 ,  H01L21/7624 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    摘要： A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.

    摘要翻译： 一种用于形成半导体结构的方法包括：提供衬底，在衬底上形成第一器件区域，形成覆盖第一器件区域的应力层，以及对第一器件区域中的应力层进行超退火，优选通过将衬底暴露于 高能量辐射源，使得应力层在超短时间内进行超退火。 优选地，该方法还包括在第一器件区域被超退火时掩蔽衬底上的第二器件区域。 或者，在第一区域中的应力层退火之后，第二器件区域中的应力层被超退火。 使用该方法形成的半导体结构在第一和第二器件区域中具有不同的应变。

    Pattern loading effect reduction for selective epitaxial growth
    7.
    发明申请
    Pattern loading effect reduction for selective epitaxial growth 审中-公开
    用于选择性外延生长的图案加载效应降低

    公开(公告)号：US20060228850A1

    公开(公告)日：2006-10-12

    申请号：US11100053

    申请日：2005-04-06

    申请人： Pang-Yen Tsai ,  Chih-Chien Chang ,  Indira Yang ,  Tze-Liang Lee ,  Shih-Chang Chen

    发明人： Pang-Yen Tsai ,  Chih-Chien Chang ,  Indira Yang ,  Tze-Liang Lee ,  Shih-Chang Chen

    IPC分类号： H01L21/8238 ,  H01L21/76

    CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66628

    摘要： A method of reducing the pattern-loading effect for selective epitaxial growth. The method includes the steps of: forming a mask layer over a substrate; forming an isolation region in the substrate isolating an active region and a dummy active region; removing at least a portion of the mask layer in the active region and thus forming a first opening, the substrate being exposed through the first opening; removing at least a portion of the mask layer in the dummy active region and thus forming a second opening, the substrate being exposed through the second opening; and performing selective epitaxial growth simultaneously on the substrate in the first opening and second openings. By introducing the second opening wherein epitaxial growth occurs, the pattern density is more uniform and thus the pattern-loading effect is reduced.

    摘要翻译： 降低选择性外延生长的图案负载效应的方法。 该方法包括以下步骤：在衬底上形成掩模层; 在所述衬底中形成隔离有源区和虚拟有源区的隔离区; 去除所述有源区域中的所述掩模层的至少一部分，从而形成第一开口，所述基板通过所述第一开口露出; 去除所述虚拟有源区域中的所述掩模层的至少一部分，从而形成第二开口，所述基板通过所述第二开口露出; 以及在所述第一开口和所述第二开口中的所述衬底上同时执行选择性外延生长。 通过引入其中发生外延生长的第二开口，图案密度更均匀，因此图案加载效应降低。

    Method of depositing an epitaxial layer of SiGe subsequent to a plasma etch
    9.
    发明授权
    Method of depositing an epitaxial layer of SiGe subsequent to a plasma etch 有权
    在等离子体蚀刻之后沉积SiGe的外延层的方法

    公开(公告)号：US07129184B2

    公开(公告)日：2006-10-31

    申请号：US11001384

    申请日：2004-12-01

    申请人： Chih-Chien Chang ,  Shun Wu Lin ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

    发明人： Chih-Chien Chang ,  Shun Wu Lin ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

    IPC分类号： H01L21/302

    CPC分类号： H01L21/02658 ,  H01L21/02381 ,  H01L21/02532

    摘要： A method of preparing a silicon layer or substrate surface for growing an epitaxial layer of SiGe thereon. The process comprises removing native oxide from the surface of the silicon with an HF solution, and then oxidizing the exposed silicon surface to form a chemically formed layer of silicon oxide of the process damaged silicon surface. The chemically formed layer of silicon oxide is then removed by a second HF cleaning process so as to leave a smooth silicon surface suitable for growing a SiGe layer.

    摘要翻译： 一种制备用于在其上生长SiGe的外延层的硅层或衬底表面的方法。 该方法包括用HF溶液从硅表面除去天然氧化物，然后氧化暴露的硅表面以形成工艺损坏的硅表面的化学形成的氧化硅层。 然后通过第二HF清洗工艺除去化学形成的氧化硅层，以便留下适于生长SiGe层的光滑硅表面。

    Multi-step epitaxial process for depositing Si/SiGe
    10.
    发明申请
    Multi-step epitaxial process for depositing Si/SiGe 有权
    用于沉积Si / SiGe的多步外延工艺

    公开(公告)号：US20070148919A1

    公开(公告)日：2007-06-28

    申请号：US11313768

    申请日：2005-12-22

    申请人： Li-Te Lin ,  Pang-Yen Tsai ,  Chih-Chien Chang ,  Tze-Liang Lee

    发明人： Li-Te Lin ,  Pang-Yen Tsai ,  Chih-Chien Chang ,  Tze-Liang Lee

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L21/02639 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661

    摘要： A method for manufacturing a semiconductor device includes providing a substrate comprising silicon, cleaning the substrate, performing a first low pressure chemical vapor deposition (LPCVD) process using a first source gas to selectively deposit a seeding layer of silicon (Si) over the substrate, performing a second LPCVD process using a second source gas to selectively deposit a first layer of silicon germanium (SiGe) over the layer of Si, the second source gas including hydrochloride at a first flow rate, and performing a third LPCVD process using a third source gas including hydrochloride at a second flow rate. The first flow rate is substantially lower than the second flow rate.

    摘要翻译： 一种制造半导体器件的方法包括提供包括硅的衬底，清洁衬底，使用第一源气体执行第一低压化学气相沉积（LPCVD）工艺，以在衬底上选择性地沉积硅（Si）晶种层， 使用第二源气体执行第二LPCVD处理，以选择性地在所述Si层上沉积第一层硅锗（SiGe），所述第二源气体以第一流速包括盐酸盐，并且使用第三源进行第三LPCVD处理 气体包括盐酸盐以第二流量。 第一流速基本上低于第二流量。