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    Output buffer of source driver
    1.
    发明授权
    Output buffer of source driver 有权
    源驱动器的输出缓冲器

    公开(公告)号：US08736373B2

    公开(公告)日：2014-05-27

    申请号：US13435340

    申请日：2012-03-30

    申请人： Chien-Ming Chen ,  Yann-Hsiung Liang ,  Hui-Wen Miao ,  Ko-Yang Tso

    发明人： Chien-Ming Chen ,  Yann-Hsiung Liang ,  Hui-Wen Miao ,  Ko-Yang Tso

    IPC分类号： H03F3/45 ,  G06F3/038

    CPC分类号： H03F3/45183 ,  G09G3/3674 ,  G09G2310/0291

    摘要： An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a ground voltage (AGND). The comparator compares an input voltage and an output voltage and outputs a control signal to the bias current source according to the compared result to control a bias current outputted by the bias current source to enhance the slew rate of the output buffer.

    摘要翻译： 公开了一种源驱动器的输出缓冲器。 输出缓冲器包括缓冲器输入，缓冲器输出，差分输入级，偏置电流源，输出级，补偿电容和比较器。 输出级和比较器均在模拟电源电压（AVDD）和接地电压（AGND）之间运行。 比较器比较输入电压和输出电压，并根据比较结果向偏置电流源输出控制信号，以控制偏置电流源输出的偏置电流，以提高输出缓冲器的转换速率。

    OUTPUT BUFFER OF SOURCE DRIVER
    2.
    发明申请
    OUTPUT BUFFER OF SOURCE DRIVER 有权
    源驱动器的输出缓冲器

    公开(公告)号：US20120249245A1

    公开(公告)日：2012-10-04

    申请号：US13435340

    申请日：2012-03-30

    申请人： Chien-Ming Chen ,  Yann-Hsiung Liang ,  Hui-Wen Miao ,  Ko-Yang Tso

    发明人： Chien-Ming Chen ,  Yann-Hsiung Liang ,  Hui-Wen Miao ,  Ko-Yang Tso

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45183 ,  G09G3/3674 ,  G09G2310/0291

    摘要： An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a ground voltage (AGND). The comparator compares an input voltage and an output voltage and outputs a control signal to the bias current source according to the compared result to control a bias current outputted by the bias current source to enhance the slew rate of the output buffer.

    摘要翻译： 公开了一种源驱动器的输出缓冲器。 输出缓冲器包括缓冲器输入，缓冲器输出，差分输入级，偏置电流源，输出级，补偿电容和比较器。 输出级和比较器均在模拟电源电压（AVDD）和接地电压（AGND）之间运行。 比较器比较输入电压和输出电压，并根据比较结果向偏置电流源输出控制信号，以控制偏置电流源输出的偏置电流，以提高输出缓冲器的转换速率。

    Output buffer of source driver
    3.
    发明授权
    Output buffer of source driver 有权
    源驱动器的输出缓冲器

    公开(公告)号：US08736372B2

    公开(公告)日：2014-05-27

    申请号：US13435322

    申请日：2012-03-30

    申请人： Chien-Ming Chen ,  Yann-Hsiung Liang ,  Hui-Wen Miao ,  Ko-Yang Tso

    发明人： Chien-Ming Chen ,  Yann-Hsiung Liang ,  Hui-Wen Miao ,  Ko-Yang Tso

    IPC分类号： H03F3/45 ,  G06F3/038

    CPC分类号： H03F3/45183 ,  G09G3/3674 ,  G09G2310/0291

    摘要： An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a half analog supply voltage (HAVDD), or both operated between the half analog supply voltage (HAVDD) and a ground voltage. The comparator compares an input signal with an output signal and outputs a control signal to the bias current source according to the compared result.

    摘要翻译： 公开了一种源驱动器的输出缓冲器。 输出缓冲器包括缓冲器输入，缓冲器输出，差分输入级，偏置电流源，输出级，补偿电容和比较器。 输出级和比较器均在模拟电源电压（AVDD）和一半模拟电源电压（HAVDD）之间运行，或两者在半模拟电源电压（HAVDD）和接地电压之间运行。 比较器将输入信号与输出信号进行比较，并根据比较结果向偏置电流源输出控制信号。

    OUTPUT BUFFER OF SOURCE DRIVER
    4.
    发明申请
    OUTPUT BUFFER OF SOURCE DRIVER 有权
    源驱动器的输出缓冲器

    公开(公告)号：US20120249244A1

    公开(公告)日：2012-10-04

    申请号：US13435322

    申请日：2012-03-30

    申请人： Chien-Ming Chen ,  Yann-Hsiung Liang ,  Hui-Wen Miao ,  Ko-Yang Tso

    发明人： Chien-Ming Chen ,  Yann-Hsiung Liang ,  Hui-Wen Miao ,  Ko-Yang Tso

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45183 ,  G09G3/3674 ,  G09G2310/0291

    摘要： An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a half analog supply voltage (HAVDD), or both operated between the half analog supply voltage (HAVDD) and a ground voltage. The comparator compares an input signal with an output signal and outputs a control signal to the bias current source according to the compared result.

    摘要翻译： 公开了一种源驱动器的输出缓冲器。 输出缓冲器包括缓冲器输入，缓冲器输出，差分输入级，偏置电流源，输出级，补偿电容和比较器。 输出级和比较器均在模拟电源电压（AVDD）和一半模拟电源电压（HAVDD）之间运行，或两者在半模拟电源电压（HAVDD）和接地电压之间运行。 比较器将输入信号与输出信号进行比较，并根据比较结果向偏置电流源输出控制信号。

    Driving Circuit and Output Buffer
    5.
    发明申请
    Driving Circuit and Output Buffer 审中-公开
    驱动电路和输出缓冲器

    公开(公告)号：US20110122102A1

    公开(公告)日：2011-05-26

    申请号：US12900236

    申请日：2010-10-07

    申请人： Ko-Yang Tso ,  Hui-Wen Miao ,  Yu-Lung Lo ,  Yann-Hsiung Liang ,  Hsin-Yeh Wu

    发明人： Ko-Yang Tso ,  Hui-Wen Miao ,  Yu-Lung Lo ,  Yann-Hsiung Liang ,  Hsin-Yeh Wu

    IPC分类号： G06F3/038

    CPC分类号： G09G3/3614 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0291

    摘要： An output buffer including a first switch circuit and a buffer is provided. The first switch circuit receives first and second input signals. The buffer circuit includes first and second input stages, first and second output stages and a second switch circuit. The first and the second input stages are coupled to the first switch circuit. The first and the second output stages are coupled to the second switch circuit. The second switch circuit, coupled to the first and the second input stages and the first and the second output stages, selectively couples one of first and the second input stages to the first output stage and selectively couples the other to the second output stage. The first switch circuit further selectively provides one of the first and the second input signals to the first input stage and selectively provides the other to the second input stage.

    摘要翻译： 提供包括第一开关电路和缓冲器的输出缓冲器。 第一开关电路接收第一和第二输入信号。 缓冲电路包括第一和第二输入级，第一和第二输出级和第二开关电路。 第一和第二输入级耦合到第一开关电路。 第一和第二输出级耦合到第二开关电路。 耦合到第一和第二输入级以及第一和第二输出级的第二开关电路选择性地将第一和第二输入级之一耦合到第一输出级，并且将另一个输入级选择性地耦合到第二输出级。 第一开关电路还选择性地将第一和第二输入信号之一提供给第一输入级，并且选择性地将另一个提供给第二输入级。

    DISPLAY DRIVER AND FLICKER SUPPRESSION DEVICE THEREOF
    8.
    发明申请
    DISPLAY DRIVER AND FLICKER SUPPRESSION DEVICE THEREOF 审中-公开
    显示驱动器和闪光灯抑制装置

    公开(公告)号：US20120280966A1

    公开(公告)日：2012-11-08

    申请号：US13439065

    申请日：2012-04-04

    申请人： Chien-Ming Chen ,  Hui-Wen Miao ,  Ko-Yang Tso

    发明人： Chien-Ming Chen ,  Hui-Wen Miao ,  Ko-Yang Tso

    IPC分类号： G09G5/00

    CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2230/00 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2320/0247 ,  G09G2330/04

    摘要： A flicker suppression device applied in a display driver for preventing the output image data of the display driver from being affected by an electrostatic discharge (ESD) event is provided. The flicker suppression device includes an ESD detector and an output stage controller. The ESD detector is coupled to a first power wire of the display driver for determining whether an ESD level shift event occurs to the first system reference voltage signal on the first power wire. If so, a control signal corresponding to the first level is provided. The output stage controller controls the output stage circuit of the display driver to be in a high impedance state in response to the control signal corresponding to the first level to avoid the output stage circuit outputting an output image data that has been affected by an ESD event.

    摘要翻译： 提供了一种应用于显示驱动器中以防止显示驱动器的输出图像数据受静电放电（ESD）事件影响的闪烁抑制装置。 闪烁抑制装置包括ESD检测器和输出级控制器。 ESD检测器耦合到显示驱动器的第一电源线，用于确定第一电源线上的第一系统参考电压信号是否发生ESD电平移位事件。 如果是，则提供对应于第一级的控制信号。 输出级控制器响应于对应于第一电平的控制信号而控制显示驱动器的输出级电路处于高阻抗状态，以避免输出级电路输出已经受ESD事件影响的输出图像数据 。

    Receiving circuit and method thereof
    9.
    发明申请
    Receiving circuit and method thereof 有权
    接收电路及其方法

    公开(公告)号：US20080253482A1

    公开(公告)日：2008-10-16

    申请号：US12073196

    申请日：2008-03-03

    申请人： Chih-Yu Lee ,  Yong-Nien Rao ,  Ko-Yang Tso ,  Hui-Wen Miao ,  Chin-Chieh Chao

    发明人： Chih-Yu Lee ,  Yong-Nien Rao ,  Ko-Yang Tso ,  Hui-Wen Miao ,  Chin-Chieh Chao

    IPC分类号： H03K9/00 ,  H04L27/00

    CPC分类号： H04L25/0292 ,  H04L25/0272

    摘要： A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.

    摘要翻译： 提供接收电路，用于接收作为RSDS信号的数据信号和时钟信号，并将输出数据信号输出到数据驱动器。 接收电路包括数据比较器，数据中间电路，时钟比较器，时钟中间和触发器。 由数据偏置电流驱动的数据比较器接收数据信号，并输出比较的数据信号。 由时钟偏置电流驱动的时钟比较器接收时钟信号，并输出比较的时钟信号。 触发器经由时钟中间电路经由数据中间电路和经比较的时钟信号接收比较的数据信号。 通过调整数据和时钟偏置电流，改善了比较数据信号与比较时钟信号之间的相位差。

    SOURCE DRIVER AND RECEIVER THEREOF
    10.
    发明申请
    SOURCE DRIVER AND RECEIVER THEREOF 有权
    源驱动器及其接收器

    公开(公告)号：US20120256660A1

    公开(公告)日：2012-10-11

    申请号：US13441211

    申请日：2012-04-06

    申请人： Ren-Feng Huang ,  Hui-Wen Miao ,  Ko-Yang Tso

    发明人： Ren-Feng Huang ,  Hui-Wen Miao ,  Ko-Yang Tso

    IPC分类号： H03K3/00

    CPC分类号： G09G3/3685 ,  G09G2330/021

    摘要： A source driver and a receiver thereof are disclosed. A two-stage amplifier of the receiver includes a first-stage circuit and a second-stage circuit. The second-stage circuit includes a first switch, a second switch, a third switch, a first node, and a second node. The first switch is coupled between the first node and a ground end; the second switch is coupled between the second node and the ground end; the third switch is coupled between the first node and the second node. When the receiver wants to wake up from a power-saving mode to a normal operation mode, the first switch and the second switch are switched to the off-state according to a control signal at first; after a period of delay time, the third switch is also switched to the off-state according to a delayed control signal.

    摘要翻译： 公开了一种源极驱动器及其接收器。 接收机的两级放大器包括第一级电路和第二级电路。 第二级电路包括第一开关，第二开关，第三开关，第一节点和第二节点。 第一开关耦合在第一节点和地端之间; 第二开关耦合在第二节点和地端之间; 第三开关耦合在第一节点和第二节点之间。 当接收机想要从省电模式唤醒到正常工作模式时，第一开关和第二开关首先根据控制信号切换到断开状态; 在延迟时间段之后，根据延迟的控制信号，第三开关也切换到断开状态。