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1.发明授权Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权采用埋入导电层的特征，用于电抗保险丝应用的电介质公开(公告)号：US07927995B2
公开(公告)日：2011-04-19
申请号：US12541502
申请日：2009-08-14
IPC分类号： H01L21/44
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译： 提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。 根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。 当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。 也可以通过增加局部温度来加速相邻互连之间的电阻的降低。
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2.发明申请公开(公告)号：US20090305493A1
公开(公告)日：2009-12-10
申请号：US12541502
申请日：2009-08-14
IPC分类号： H01L21/768
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译： 提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。 根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。 当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。 也可以通过增加局部温度来加速相邻互连之间的电阻的降低。
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3.发明申请公开(公告)号：US20080283964A1
公开(公告)日：2008-11-20
申请号：US12144229
申请日：2008-06-23
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译： 提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。 根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。 当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。 也可以通过增加局部温度来加速相邻互连之间的电阻的降低。
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4.发明授权Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权采用埋入导电层的特征，用于电抗保险丝应用的电介质公开(公告)号：US07402463B2
公开(公告)日：2008-07-22
申请号：US11207218
申请日：2005-08-19
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译： 提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。 根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。 当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。 也可以通过增加局部温度来加速相邻互连之间的电阻的降低。
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5.发明授权Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权采用埋入导电层的特征，用于电抗保险丝应用的电介质公开(公告)号：US08159042B2
公开(公告)日：2012-04-17
申请号：US12144229
申请日：2008-06-23
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译： 提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。 根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。 当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。 也可以通过增加局部温度来加速相邻互连之间的电阻的降低。
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公开(公告)号：US07528065B2
公开(公告)日：2009-05-05
申请号：US11333068
申请日：2006-01-17
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译： 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。
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公开(公告)号：US07105445B2
公开(公告)日：2006-09-12
申请号：US11034890
申请日：2005-01-14
申请人： Kwong-Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carl J. Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
发明人： Kwong-Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carl J. Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
IPC分类号： H01L21/44
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译： 一种制造互连的方法，其包括在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸，并且在所述互连结构的所述延伸部分上沉积包封盖 。
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公开(公告)号：US08304912B2
公开(公告)日：2012-11-06
申请号：US12054644
申请日：2008-03-25
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译： 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅电极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。
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公开(公告)号：US07902061B2
公开(公告)日：2011-03-08
申请号：US12199407
申请日：2008-08-27
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Theodorus E. Standaert , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu , Carl Radens , Theodorus E. Standaert , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect structure: which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric material; and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译： 一种制造互连结构的方法，其包括在介电材料中提供互连结构，使介电材料凹陷，使得互连结构的一部分在电介质材料的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。
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10.发明申请公开(公告)号：US20080318415A1
公开(公告)日：2008-12-25
申请号：US12199407
申请日：2008-08-27
申请人： Kwong Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carl Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
发明人： Kwong Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carl Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译： 一种制造互连的方法，包括：在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。
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