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    Hybrid interconnect structure for performance improvement and reliability enhancement
    1.
    发明授权
    Hybrid interconnect structure for performance improvement and reliability enhancement 有权
    混合互连结构，用于性能改进和可靠性提升

    公开(公告)号：US07973409B2

    公开(公告)日：2011-07-05

    申请号：US11625576

    申请日：2007-01-22

    申请人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

    摘要翻译： 本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地， 气隙。 与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。 此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

    HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT
    2.
    发明申请
    HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT 有权
    混合互连结构，用于性能改进和可靠性增强

    公开(公告)号：US20080174017A1

    公开(公告)日：2008-07-24

    申请号：US11625576

    申请日：2007-01-22

    申请人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

    摘要翻译： 本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地， 气隙。 与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。 此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

    Hybrid interconnect structure for performance improvement and reliability enhancement
    3.
    发明授权
    Hybrid interconnect structure for performance improvement and reliability enhancement 有权
    混合互连结构，用于性能改进和可靠性提升

    公开(公告)号：US08456006B2

    公开(公告)日：2013-06-04

    申请号：US13174841

    申请日：2011-07-01

    申请人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

    摘要翻译： 本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地， 气隙。 与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。 此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

    HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD
    4.
    发明申请
    HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD 有权
    高比例电镀金属特征及方法

    公开(公告)号：US20100143649A1

    公开(公告)日：2010-06-10

    申请号：US12706108

    申请日：2010-02-16

    申请人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

    发明人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

    IPC分类号： B32B3/10

    CPC分类号： C25D5/02 ,  Y10T428/24331 ,  Y10T428/24917

    摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

    摘要翻译： 公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料 没有接缝和/或空隙。 此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层 金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

    REVERSIBLE ELECTRIC FUSE AND ANTIFUSE STRUCTURES FOR SEMICONDUCTOR DEVICES
    6.
    发明申请
    REVERSIBLE ELECTRIC FUSE AND ANTIFUSE STRUCTURES FOR SEMICONDUCTOR DEVICES 有权
    用于半导体器件的可逆电源保险丝和抗反射结构

    公开(公告)号：US20080157269A1

    公开(公告)日：2008-07-03

    申请号：US11619264

    申请日：2007-01-03

    申请人： Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

    发明人： Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

    IPC分类号： H01L29/00 ,  H01L21/02

    CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method of fabricating reversible fuse and antifuse structures for semiconductor devices is provided. In one embodiment, the method includes forming at least one line having a via opening for exposing a portion of a plurality of interconnect features; conformally depositing a first material layer over the via opening; depositing a second material layer over the first material layer, wherein the depositing overhangs a portion of the second material layer on a top portion of the via opening; and depositing a blanket layer of insulating material, where the depositing forms a plurality of fuse elements each having an airgap between the insulating material and the second material layer. The method further includes forming a plurality of electroplates in the insulator material connecting the fuse elements. In another embodiment, the method includes depositing a first and a second material layer on a semiconductor substrate, wherein the second material layer having a higher electrical conductivity than the first material layer; selectively etching the first and second material layer to create at least one constricted region to facilitate electromigration of the second material; wherein the electromigration creates a plurality of micro voids; and forming a plurality of electrical contacts on the second material layer.

    摘要翻译： 提供一种用于制造用于半导体器件的可逆熔丝和反熔丝结构的结构和方法。 在一个实施例中，该方法包括形成至少一条线，其具有用于暴露多个互连特征的一部分的通孔; 在通孔开口上共形沉积第一材料层; 在所述第一材料层上沉积第二材料层，其中所述沉积在所述通孔开口的顶部部分上突出所述第二材料层的一部分; 以及沉积绝缘材料的覆盖层，其中所述沉积形成多个熔丝元件，每个熔丝元件在所述绝缘材料和所述第二材料层之间具有气隙。 该方法还包括在连接熔丝元件的绝缘体材料中形成多个电镀层。 在另一个实施例中，该方法包括在半导体衬底上沉积第一和第二材料层，其中第二材料层具有比第一材料层更高的导电性; 选择性地蚀刻第一和第二材料层以产生至少一个收缩区域以促进第二材料的电迁移; 其中所述电迁移产生多个微空隙; 以及在所述第二材料层上形成多个电接触。