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公开(公告)号：US20090100245A1
公开(公告)日：2009-04-16
申请号：US12287961
申请日：2008-10-15
申请人： Chih-Min Wang , Chao-Ping Su , Yi-Lung Tsai , Ming-Hong Huang
发明人： Chih-Min Wang , Chao-Ping Su , Yi-Lung Tsai , Ming-Hong Huang
CPC分类号： G06F12/0284 , G06F12/109
摘要： An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the manufacture cost of the electronic system. The addressing device includes an address decoder and an address translator. The address decoder receives a first access address belonging to a smaller address space, and determines whether to map the first access address to the larger storage space of the memory device. The address translator is coupled to the address decoder. When the first access address is mapped to the storage space of the memory device, the address translator translates the first access address into a second access address of the larger storage space according to an adjustable base address.
摘要翻译： 提供了寻址装置和方法，以使具有较少寻址能力的电子系统能够寻址具有较大存储空间的存储器件，从而降低了电子系统的制造成本。 寻址装置包括地址解码器和地址转换器。 地址解码器接收属于较小地址空间的第一访问地址，并且确定是否将第一访问地址映射到存储设备的较大存储空间。 地址转换器耦合到地址解码器。 当第一访问地址被映射到存储设备的存储空间时，地址转换器根据可调基地址将第一访问地址转换为较大存储空间的第二访问地址。
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公开(公告)号：US08762683B2
公开(公告)日：2014-06-24
申请号：US12287961
申请日：2008-10-15
申请人： Chih-Min Wang , Chao-Ping Su , Yi-Lung Tsai , Ming-Hong Huang
发明人： Chih-Min Wang , Chao-Ping Su , Yi-Lung Tsai , Ming-Hong Huang
CPC分类号： G06F12/0284 , G06F12/109
摘要： An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the manufacture cost of the electronic system. The addressing device includes an address decoder and an address translator. The address decoder receives a first access address belonging to a smaller address space, and determines whether to map the first access address to the larger storage space of the memory device. The address translator is coupled to the address decoder. When the first access address is mapped to the storage space of the memory device, the address translator translates the first access address into a second access address of the larger storage space according to an adjustable base address.
摘要翻译： 提供了寻址装置和方法，以使具有较少寻址能力的电子系统能够寻址具有较大存储空间的存储器件，从而降低了电子系统的制造成本。 寻址装置包括地址解码器和地址转换器。 地址解码器接收属于较小地址空间的第一访问地址，并且确定是否将第一访问地址映射到存储设备的较大存储空间。 地址转换器耦合到地址解码器。 当第一访问地址被映射到存储设备的存储空间时，地址转换器根据可调基地址将第一访问地址转换为较大存储空间的第二访问地址。
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公开(公告)号：US08930665B2
公开(公告)日：2015-01-06
申请号：US12251744
申请日：2008-10-15
申请人： Chih-Min Wang , Chao-ping Su , Shih-Jan Wei , Ming-Hong Huang
发明人： Chih-Min Wang , Chao-ping Su , Shih-Jan Wei , Ming-Hong Huang
CPC分类号： G06F1/3225 , G06F1/10 , G06F13/4234 , G06F2213/16
摘要： A data access system and a data access method achieving effects of power saving and access synchronization during data access are provided. The data access system includes a data processing unit, a bridge device and a memory device. The data processing unit sends an access request signal to initiate data access of at least one unit data. The access of unit data is completed within a plurality of clock cycles of a reference clock signal. The bridge device generates an access signal according to the access request signal, the reference clock signal and a leading time. A pulse of the access signal is determined by the leading time within the clock cycles. The memory device executes the access of the unit data according to the access signal.
摘要翻译： 提供了一种在数据访问期间实现节电和访问同步的数据访问系统和数据访问方法。 数据访问系统包括数据处理单元，桥接器件和存储器件。 数据处理单元发送访问请求信号以启动至少一个单元数据的数据访问。 单元数据的访问在参考时钟信号的多个时钟周期内完成。 桥接器件根据访问请求信号，参考时钟信号和引导时间生成访问信号。 接入信号的脉冲由时钟周期内的引导时间决定。 存储器件根据访问信号执行单元数据的访问。
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公开(公告)号：US20090100234A1
公开(公告)日：2009-04-16
申请号：US12251744
申请日：2008-10-15
申请人： Chih-Min Wang , Chao-Ping Su , Shih-Jan Wei , Ming-Hong Huang
发明人： Chih-Min Wang , Chao-Ping Su , Shih-Jan Wei , Ming-Hong Huang
CPC分类号： G06F1/3225 , G06F1/10 , G06F13/4234 , G06F2213/16
摘要： A data access system and a data access method achieving effects of power saving and access synchronization during data access are provided. The data access system includes a data processing unit, a bridge device and a memory device. The data processing unit sends an access request signal to initiate data access of at least one unit data. The access of unit data is completed within a plurality of clock cycles of a reference clock signal. The bridge device generates an access signal according to the access request signal, the reference clock signal and a leading time. A pulse of the access signal is determined by the leading time within the clock cycles. The memory device executes the access of the unit data according to the access signal.
摘要翻译： 提供了一种在数据访问期间实现节电和访问同步的数据访问系统和数据访问方法。 数据访问系统包括数据处理单元，桥接器件和存储器件。 数据处理单元发送访问请求信号以启动至少一个单元数据的数据访问。 单元数据的访问在参考时钟信号的多个时钟周期内完成。 桥接器件根据访问请求信号，参考时钟信号和引导时间生成访问信号。 接入信号的脉冲由时钟周期内的引导时间决定。 存储器件根据访问信号执行单元数据的访问。
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