公开(公告)号：US08930665B2

公开(公告)日：2015-01-06

申请号：US12251744

申请日：2008-10-15

申请人： Chih-Min Wang ,  Chao-ping Su ,  Shih-Jan Wei ,  Ming-Hong Huang

发明人： Chih-Min Wang ,  Chao-ping Su ,  Shih-Jan Wei ,  Ming-Hong Huang

IPC分类号： G06F13/42 ,  G06F1/32 ,  G06F1/10

CPC分类号： G06F1/3225 ,  G06F1/10 ,  G06F13/4234 ,  G06F2213/16

摘要： A data access system and a data access method achieving effects of power saving and access synchronization during data access are provided. The data access system includes a data processing unit, a bridge device and a memory device. The data processing unit sends an access request signal to initiate data access of at least one unit data. The access of unit data is completed within a plurality of clock cycles of a reference clock signal. The bridge device generates an access signal according to the access request signal, the reference clock signal and a leading time. A pulse of the access signal is determined by the leading time within the clock cycles. The memory device executes the access of the unit data according to the access signal.

摘要翻译： 提供了一种在数据访问期间实现节电和访问同步的数据访问系统和数据访问方法。 数据访问系统包括数据处理单元，桥接器件和存储器件。 数据处理单元发送访问请求信号以启动至少一个单元数据的数据访问。 单元数据的访问在参考时钟信号的多个时钟周期内完成。 桥接器件根据访问请求信号，参考时钟信号和引导时间生成访问信号。 接入信号的脉冲由时钟周期内的引导时间决定。 存储器件根据访问信号执行单元数据的访问。

公开(公告)号：US08762683B2

公开(公告)日：2014-06-24

申请号：US12287961

申请日：2008-10-15

申请人： Chih-Min Wang ,  Chao-Ping Su ,  Yi-Lung Tsai ,  Ming-Hong Huang

发明人： Chih-Min Wang ,  Chao-Ping Su ,  Yi-Lung Tsai ,  Ming-Hong Huang

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0284 ,  G06F12/109

摘要： An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the manufacture cost of the electronic system. The addressing device includes an address decoder and an address translator. The address decoder receives a first access address belonging to a smaller address space, and determines whether to map the first access address to the larger storage space of the memory device. The address translator is coupled to the address decoder. When the first access address is mapped to the storage space of the memory device, the address translator translates the first access address into a second access address of the larger storage space according to an adjustable base address.

摘要翻译： 提供了寻址装置和方法，以使具有较少寻址能力的电子系统能够寻址具有较大存储空间的存储器件，从而降低了电子系统的制造成本。 寻址装置包括地址解码器和地址转换器。 地址解码器接收属于较小地址空间的第一访问地址，并且确定是否将第一访问地址映射到存储设备的较大存储空间。 地址转换器耦合到地址解码器。 当第一访问地址被映射到存储设备的存储空间时，地址转换器根据可调基地址将第一访问地址转换为较大存储空间的第二访问地址。

公开(公告)号：US20090217257A1

公开(公告)日：2009-08-27

申请号：US12392284

申请日：2009-02-25

申请人： Ming Hong Huang ,  Chao Ping Su ,  Chih Chieh Lee

发明人： Ming Hong Huang ,  Chao Ping Su ,  Chih Chieh Lee

IPC分类号： G06F9/44 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F8/65 ,  G06F8/654

摘要： An apparatus and a method for firmware update to provide reliable firmware update for electronic devices, thereby improving user convenience. A firmware update apparatus includes a first storage unit, a second storage unit, a checking unit and a controller. The first and second storage units store first and second firmware codes of an electronic device, respectively. The checking unit checks whether the second firmware code is valid. The microcontroller initiates the checking unit upon start of the electronic device, and determines whether to execute the second firmware code upon determining the validity of the second firmware code.

摘要翻译： 一种用于固件更新的装置和方法，用于为电子设备提供可靠的固件更新，从而提高用户便利性。 固件更新装置包括第一存储单元，第二存储单元，检查单元和控制器。 第一和第二存储单元分别存储电子设备的第一和第二固件代码。 检查单元检查第二固件代码是否有效。 微控制器在电子设备启动时启动检查单元，并且在确定第二固件代码的有效性时确定是否执行第二固件代码。

公开(公告)号：US20090100234A1

公开(公告)日：2009-04-16

申请号：US12251744

申请日：2008-10-15

申请人： Chih-Min Wang ,  Chao-Ping Su ,  Shih-Jan Wei ,  Ming-Hong Huang

发明人： Chih-Min Wang ,  Chao-Ping Su ,  Shih-Jan Wei ,  Ming-Hong Huang

IPC分类号： G06F12/00 ,  G06F1/04

CPC分类号： G06F1/3225 ,  G06F1/10 ,  G06F13/4234 ,  G06F2213/16

摘要： A data access system and a data access method achieving effects of power saving and access synchronization during data access are provided. The data access system includes a data processing unit, a bridge device and a memory device. The data processing unit sends an access request signal to initiate data access of at least one unit data. The access of unit data is completed within a plurality of clock cycles of a reference clock signal. The bridge device generates an access signal according to the access request signal, the reference clock signal and a leading time. A pulse of the access signal is determined by the leading time within the clock cycles. The memory device executes the access of the unit data according to the access signal.

摘要翻译： 提供了一种在数据访问期间实现节电和访问同步的数据访问系统和数据访问方法。 数据访问系统包括数据处理单元，桥接器件和存储器件。 数据处理单元发送访问请求信号以启动至少一个单元数据的数据访问。 单元数据的访问在参考时钟信号的多个时钟周期内完成。 桥接器件根据访问请求信号，参考时钟信号和引导时间生成访问信号。 接入信号的脉冲由时钟周期内的引导时间决定。 存储器件根据访问信号执行单元数据的访问。

公开(公告)号：US20090100245A1

公开(公告)日：2009-04-16

申请号：US12287961

申请日：2008-10-15

申请人： Chih-Min Wang ,  Chao-Ping Su ,  Yi-Lung Tsai ,  Ming-Hong Huang

发明人： Chih-Min Wang ,  Chao-Ping Su ,  Yi-Lung Tsai ,  Ming-Hong Huang

IPC分类号： G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0284 ,  G06F12/109

摘要： An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the manufacture cost of the electronic system. The addressing device includes an address decoder and an address translator. The address decoder receives a first access address belonging to a smaller address space, and determines whether to map the first access address to the larger storage space of the memory device. The address translator is coupled to the address decoder. When the first access address is mapped to the storage space of the memory device, the address translator translates the first access address into a second access address of the larger storage space according to an adjustable base address.

摘要翻译： 提供了寻址装置和方法，以使具有较少寻址能力的电子系统能够寻址具有较大存储空间的存储器件，从而降低了电子系统的制造成本。 寻址装置包括地址解码器和地址转换器。 地址解码器接收属于较小地址空间的第一访问地址，并且确定是否将第一访问地址映射到存储设备的较大存储空间。 地址转换器耦合到地址解码器。 当第一访问地址被映射到存储设备的存储空间时，地址转换器根据可调基地址将第一访问地址转换为较大存储空间的第二访问地址。

公开(公告)号：US20090249320A1

公开(公告)日：2009-10-01

申请号：US12372956

申请日：2009-02-18

申请人： CHAO PING SU ,  MING HONG HUANG ,  CHIH CHIEH LEE ,  KUN NAN CHENG

发明人： CHAO PING SU ,  MING HONG HUANG ,  CHIH CHIEH LEE ,  KUN NAN CHENG

IPC分类号： G06F9/44

CPC分类号： G06F8/65

摘要： A display control device with automatic firmware update and an update method thereof are provided to update the firmware of the display control device rapidly and automatically, thereby improving user convenience and reducing user waiting time. The display control device comprises a transmission interface unit, a memory interface unit, a non-volatile memory interface unit, a first direct memory access (DMA) unit, a second DMA unit and a controller. The transmission interface unit is coupled to a code-providing unit for providing an updated code of the firmware. After detecting that the transmission interface unit is coupled to the code-proving unit, the controller automatically and temporarily stores the updated code provided by the code-providing unit into a dynamic random access memory (DRAM), and further writes the updated code into a non-volatile memory from the DRAM, thereby accomplishing automatic update of the firmware of the display control device.

摘要翻译： 提供具有自动固件更新的显示控制装置及其更新方法，以快速且自动地更新显示控制装置的固件，从而提高用户便利性并减少用户等待时间。 显示控制装置包括传输接口单元，存储器接口单元，非易失性存储器接口单元，第一直接存储器访问（DMA）单元，第二DMA单元和控制器。 传输接口单元耦合到用于提供固件的更新代码的代码提供单元。 在检测到传输接口单元耦合到代码验证单元之后，控制器将由代码提供单元提供的更新的代码自动暂时存储到动态随机存取存储器（DRAM）中，并且将更新后的代码写入到 非易失性存储器，从而实现显示控制装置的固件的自动更新。

公开(公告)号：US20070174680A1

公开(公告)日：2007-07-26

申请号：US11414331

申请日：2006-05-01

申请人： Chao-Ping Su ,  Ching-Han Hsiao

发明人： Chao-Ping Su ,  Ching-Han Hsiao

IPC分类号： G06F11/00

CPC分类号： G06F8/66

摘要： The invention discloses a patching method to correct the built-in code in read only memory (ROM), which loads the patching address stored in an external storage device and the patching content into a register and a RAM respectively. When the executing sequence reaches the patching address in the ROM, the sequence of executing jumps to the RAM to perform the patching content. After executing the patching content, the executing switches back to the ROM to execute the original executing sequence, with the present invention, the ROM chip is not necessary to be replaced when the content in the ROM needs to be corrected.

摘要翻译： 本发明公开了一种修正只读存储器（ROM）中的内置代码的修补方法，它将存储在外部存储设备中的修补地址和修补内容分别加载到寄存器和RAM中。 当执行顺序到达ROM中的修补地址时，执行顺序跳转到RAM以执行修补内容。 在执行修补内容之后，执行切换回ROM以执行原始执行顺序，通过本发明，当需要修正ROM中的内容时，不需要更换ROM芯片。