公开(公告)号：US20080143446A1

公开(公告)日：2008-06-19

申请号：US11957482

申请日：2007-12-17

申请人： Chih-Wei Yao ,  Alan Neil Willson

发明人： Chih-Wei Yao ,  Alan Neil Willson

IPC分类号： H03B27/00 ,  H03B5/12

CPC分类号： H03B27/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1253 ,  H03B2200/0074

摘要： A tail-tank coupling technique combines two complementary differential LC-VCOs to form a quadrature LC-VCO. The technique reduces phase noise by providing additional energy storage for noise redistribution and by cancelling noise injected by transistors when they operate in the triode region. The resulting noise factor is close to the theoretical minimum 1+γ, similar to a differential LC-VCO driven by an ideal noiseless current source. However, its figure-of-merit is higher, due to the absence of voltage head-room being consumed by a current source. The optimal ratio of tail-tank capacitor to main-tank capacitor for minimizing phase noise is approximately 0.5. The method can be extended to combine any even number of LC tanks resonating at fo and 2fo to form an integrated oscillator producing quadrature phase at frequency fosc and differential output at 2fosc.

摘要翻译： 尾箱耦合技术结合了两个互补的差分LC-VCO来形成正交LC-VCO。 该技术通过为噪声再分配提供额外的能量存储并通过消除晶体管在三极管区域中工作时注入的噪声来降低相位噪声。 所产生的噪声系数接近理论最小值1 +γ，类似于由理想无噪声电流源驱动的差分LC-VCO。 然而，由于电流源没有电压头部消耗，其品质因数更高。 用于最小相位噪声的尾箱电容器与主柜电容器的最佳比例约为0.5。 该方法可以被扩展以组合在f 0和2 f 0上共振的任何偶数个LC槽，以形成一个在频率f osc处产生正交相位的集成振荡器， / SUB>和2f 之间的差分输出。

公开(公告)号：US07847650B2

公开(公告)日：2010-12-07

申请号：US11957482

申请日：2007-12-17

申请人： Chih-Wei Yao ,  Alan Neil Willson, Jr.

发明人： Chih-Wei Yao ,  Alan Neil Willson, Jr.

IPC分类号： H03B5/08 ,  H03B5/18

CPC分类号： H03B27/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1253 ,  H03B2200/0074

摘要： A tail-tank coupling technique combines two complementary differential LC-VCOs to form a quadrature LC-VCO. The technique reduces phase noise by providing additional energy storage for noise redistribution and by cancelling noise injected by transistors when they operate in the triode region. The resulting noise factor is close to the theoretical minimum 1+γ, similar to a differential LC-VCO driven by an ideal noiseless current source. However, its figure-of-merit is higher, due to the absence of voltage head-room being consumed by a current source. The optimal ratio of tail-tank capacitor to main-tank capacitor for minimizing phase noise is approximately 0.5. The method can be extended to combine any even number of LC tanks resonating at fo and 2fo to form an integrated oscillator producing quadrature phase at frequency fosc and differential output at 2fosc.

摘要翻译： 尾箱耦合技术结合了两个互补的差分LC-VCO来形成正交LC-VCO。 该技术通过为噪声再分配提供额外的能量存储并通过消除晶体管在三极管区域中工作时注入的噪声来降低相位噪声。 所产生的噪声系数接近理论最小值1 +γ，类似于由理想无噪声电流源驱动的差分LC-VCO。 然而，由于电流源没有电压头部消耗，其品质因数更高。 用于最小相位噪声的尾箱电容器与主柜电容器的最佳比例约为0.5。 该方法可以扩展到组合在fo和2fo共振的任何偶数个LC箱，以形成一个集成振荡器，产生频率fosc的正交相位和在2fosc处的差分输出。

公开(公告)号：US08461886B1

公开(公告)日：2013-06-11

申请号：US13277505

申请日：2011-10-20

申请人： Chih-Wei Yao

发明人： Chih-Wei Yao

IPC分类号： H03L7/06

CPC分类号： H03L7/089

摘要： A PLL includes a PFD configured to: receive a reference clock and a feedback clock, output a first signal, which includes first phase information for a rising edge of the reference clock, and output a second signal, which includes second phase information for a rising edge of the feedback clock. The PLL includes a logic gate coupled to the PFD configured to logically combine the first and second signals to produce a pulse signal having a rising edge, which includes the first phase information, and having a falling edge, which includes the second phase information. The PLL includes a TDC coupled the logic gate configured to generate a digital timing signal, which includes timing information for a phase difference of the first and second phase information. The PLL includes a controlled oscillator coupled to the TDC configured to vary a frequency of the feedback clock from the digital timing signal.

摘要翻译： PLL包括被配置为：接收参考时钟和反馈时钟的PFD，输出包括参考时钟的上升沿的第一相位信息的第一信号，并输出第二信号，该第二信号包括用于上升的第二相位信息 反馈时钟的边缘。 PLL包括耦合到PFD的逻辑门，其被配置为逻辑地组合第一和第二信号以产生具有上升沿的脉冲信号，其包括第一相位信息，并且具有包括第二相位信息的下降沿。 PLL包括耦合逻辑门的TDC，被配置为产生数字定时信号，其包括用于第一和第二相位信息的相位差的定时信息。 PLL包括耦合到TDC的受控振荡器，其被配置为从数字定时信号改变反馈时钟的频率。

公开(公告)号：US08564471B1

公开(公告)日：2013-10-22

申请号：US13333058

申请日：2011-12-21

申请人： Xiang Gao ,  Chih-Wei Yao ,  Chi-Hung Lin ,  Li Lin

发明人： Xiang Gao ,  Chih-Wei Yao ,  Chi-Hung Lin ,  Li Lin

IPC分类号： H03M1/50

CPC分类号： H03M1/50 ,  G04F10/005 ,  H03K5/13 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/0641 ,  H03M1/0695 ,  H03M1/12 ,  H03M2201/4233

摘要： Disclosed is a time-to-digital (TDC) converter comprising an analog voltage source. An analog-to-digital converter quantizes two voltage samples in response to receiving a first input signal at a first time t1 and a second input signal at a second time t2. The first and second digital signals are combined to produce a digital signal that represents the difference (t2−t1).

摘要翻译： 公开了一种包括模拟电压源的时间数字（TDC）转换器。 响应于在第一时间t1接收第一输入信号和第二时间t2的第二输入信号，模数转换器量化两个电压采样。 第一和第二数字信号被组合以产生表示差的数字信号（t2-t1）。

公开(公告)号：US20120200328A1

公开(公告)日：2012-08-09

申请号：US13364185

申请日：2012-02-01

申请人： Chih-Wei Yao

发明人： Chih-Wei Yao

IPC分类号： H03L7/08

CPC分类号： H03L7/06 ,  H03L7/1976

摘要： In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity.

摘要翻译： 在一个实施例中，一种方法包括确定用于锁相环（PLL）的偶数和奇数周期中的参考时钟和反馈时钟之间的相位差。 偶数和奇数周期是交替的时钟周期。 确定基于相位差的增量值。 然后，该方法调整除法器使用的除法值，以在偶数周期期间基于增量值为增量值为第一极性的增量值生成反馈时钟。 此外，该方法调整除法器使用的除法值，以在奇数周期内基于增量值为第二极性的增量值产生反馈时钟。

公开(公告)号：US08564342B2

公开(公告)日：2013-10-22

申请号：US13364185

申请日：2012-02-01

申请人： Chih-Wei Yao

发明人： Chih-Wei Yao

IPC分类号： H03L7/06

CPC分类号： H03L7/06 ,  H03L7/1976

摘要： In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity.

摘要翻译： 在一个实施例中，一种方法包括确定用于锁相环（PLL）的偶数和奇数周期中的参考时钟和反馈时钟之间的相位差。 偶数和奇数周期是交替的时钟周期。 确定基于相位差的增量值。 然后，该方法调整除法器使用的除法值，以在偶数周期期间基于增量值为增量值为第一极性的增量值生成反馈时钟。 此外，该方法调整除法器使用的除法值，以在奇数周期内基于增量值为第二极性的增量值产生反馈时钟。