公开(公告)号：US20160099247A1

公开(公告)日：2016-04-07

申请号：US14874897

申请日：2015-10-05

申请人： Taejin Park ,  Jemin Park ,  Daeik Kim ,  Woojin Kim ,  Kiseok Lee ,  Yoosang Hwang

发明人： Taejin Park ,  Jemin Park ,  Daeik Kim ,  Woojin Kim ,  Kiseok Lee ,  Yoosang Hwang

IPC分类号： H01L27/108 ,  H01L49/02

CPC分类号： H01L27/10814 ,  H01L28/87 ,  H01L28/91

摘要： A semiconductor device includes bottom electrodes two-dimensionally arranged on a substrate and transistors connected to the bottom electrodes, respectively. Each of the bottom electrodes may include first side surfaces facing each other in a first direction and second side surfaces facing each other in a second direction crossing the first direction. At least one of the first and second side surfaces may have a concave shape, when viewed in a plan view.

摘要翻译： 半导体器件包括二维地排列在衬底上的底部电极和分别连接到底部电极的晶体管。 每个底部电极可以包括在第一方向上彼此面对的第一侧表面和在与第一方向交叉的第二方向上彼此面对的第二侧表面。 当在平面图中观察时，第一和第二侧表面中的至少一个可以具有凹形。

公开(公告)号：US09111960B2

公开(公告)日：2015-08-18

申请号：US13242660

申请日：2011-09-23

申请人： Hui-Jung Kim ,  Yongchul Oh ,  Daeik Kim ,  Hyun-Woo Chung

发明人： Hui-Jung Kim ,  Yongchul Oh ,  Daeik Kim ,  Hyun-Woo Chung

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/108

CPC分类号： H01L29/66666 ,  H01L27/10876 ,  H01L29/7827

摘要： Semiconductor devices with vertical channel transistors, the devices including semiconductor patterns disposed on a substrate, first gate patterns disposed between the semiconductor patterns on the substrate, a second gate pattern spaced apart from the first gate patterns by the semiconductor patterns, and conductive lines crossing the first gate patterns. The second gate pattern includes a first portion extending parallel to the first gate patterns and a second portion extending parallel to the conductive lines.

摘要翻译： 具有垂直沟道晶体管的半导体器件，包括设置在衬底上的半导体图案的器件，设置在衬底上的半导体图案之间的第一栅极图案，通过半导体图案与第一栅极图案间隔开的第二栅极图案， 第一门模式。 第二栅极图案包括平行于第一栅极图案延伸的第一部分和平行于导电线延伸的第二部分。

公开(公告)号：US08438404B2

公开(公告)日：2013-05-07

申请号：US12241332

申请日：2008-09-30

申请人： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

发明人： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

IPC分类号： G06F13/00 ,  G06F7/04 ,  G06F15/173 ,  G06F9/45 ,  G06F15/00 ,  G06F9/46 ,  H04L12/28

CPC分类号： G06F9/5027 ,  G06F2209/509 ,  Y02D10/22

摘要： The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

摘要翻译： 本公开应用于具有一组（例如，一个或多个）控制元件（例如，MPE）和一组子处理元件（例如，SPE）的通用微处理器架构。 在这种安排下，MPEs和SPE的组织方式是使用较少数量的MPE使用体现为一组虚拟控制线程的程序代码控制一组SPE的行为。 该安排还使MPEs能够将功能委托给一个或多个SPE组，使得这些SPE组将充当伪MPE。 伪MPE将利用伪虚拟化控制线程来控制其他组的SPE的行为。 在典型的实施例中，该装置包括耦合到与核耦合的电源的MCP以向每个核（或核心组）提供电源电压以及控制数字元件和子处理元件的多个实例。

公开(公告)号：US20120119289A1

公开(公告)日：2012-05-17

申请号：US13287304

申请日：2011-11-02

申请人： Daeik KIM

发明人： Daeik KIM

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66666

摘要： Provided is a semiconductor device including a substrate having active patterns extending between first trenches and between second trenches (the first and second trenches intersecting each other), and gate patterns disposed within the first trenches, wherein each of the active patterns includes lower and upper impurity regions, and a channel region between the lower and upper impurity regions, the lower and upper impurity regions being vertically spaced apart from each other and having a conductivity type different from the substrate, and the channel region having the same conductivity type as the substrate, and a bottom surface of the gate pattern is closer to a bottom surface of the first trench than the lower impurity region.

摘要翻译： 提供了一种半导体器件，其包括具有在第一沟槽之间并且在第二沟槽之间（第一和第二沟槽彼此交叉）之间的有源图案的衬底和设置在第一沟槽内的栅极图案，其中每个有源图案包括较低和上部杂质 下部杂质区域和上部杂质区域之间的沟道区域，下部和上部杂质区域彼此垂直间隔开并且具有不同于衬底的导电类型，并且沟道区域具有与衬底相同的导电类型， 并且栅极图案的底表面比下部杂质区域更靠近第一沟槽的底表面。

公开(公告)号：US20120086065A1

公开(公告)日：2012-04-12

申请号：US13097343

申请日：2011-04-29

申请人： Daeik KIM ,  Yongchul Oh ,  Yoosang Hwang ,  Hyun-Woo Chung ,  Young-Seung Cho

发明人： Daeik KIM ,  Yongchul Oh ,  Yoosang Hwang ,  Hyun-Woo Chung ,  Young-Seung Cho

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/108 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： Provided is a semiconductor device having a vertical channel transistor and method of fabricating the same. The semiconductor device includes first and second field effect transistors, wherein a channel region of the first field effect transistor serves as source/drain electrodes of the second field effect transistor, and a channel region of the second field effect transistor serves as source/drain electrodes of the first field effect transistor.

摘要翻译： 提供一种具有垂直沟道晶体管的半导体器件及其制造方法。 半导体器件包括第一和第二场效应晶体管，其中第一场效应晶体管的沟道区用作第二场效应晶体管的源/漏电极，第二场效应晶体管的沟道区用作源极/漏极 的第一场效应晶体管。

公开(公告)号：US07902880B2

公开(公告)日：2011-03-08

申请号：US12844339

申请日：2010-07-27

申请人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim

发明人： Choongyeun Cho ,  Daeik Kim ,  Jonghae Kim ,  Moon Ju Kim

IPC分类号： H01L25/00 ,  H03K19/00

CPC分类号： H03K19/0016 ,  Y10T29/49002

摘要： Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.

摘要翻译： 提供了电路和方法，以便于将数字电路从背栅极偏置待机模式转换到主动模式。 数字电路包括半导体衬底，至少部分地设置在半导体衬底中的一个或多个p型阱中的多个n沟道晶体管，至少部分地设置在半导体中的一个或多个n型阱中的多个p沟道晶体管 基板和背栅控制电路。 背栅控制电路电耦合到p型阱和n型阱，以便于将多个n沟道晶体管和多个p沟道晶体管从背栅极偏置待机模式转换到有源 模式，通过自动将电荷从n型阱转移到p型阱，直到达到阱电压阈值，表明晶体管从背栅极偏置待机模式到活动模式的完成转变。

公开(公告)号：US20100216293A1

公开(公告)日：2010-08-26

申请号：US12703071

申请日：2010-02-09

申请人： ByoungHo Kwon ,  Boun Yoon ,  Daeik Kim ,  Sung-Min Cho

发明人： ByoungHo Kwon ,  Boun Yoon ,  Daeik Kim ,  Sung-Min Cho

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/28123 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11575

摘要： A method for fabricating a semiconductor device includes providing a semiconductor substrate including a memory cell region and peripheral circuit regions. Gate electrodes including gate conductive patterns and capping patterns are formed on the memory cell region and the peripheral circuit regions. An interlayer dielectric covering the gate electrodes is formed. The interlayer dielectric is patterned to form first contact holes exposing the semiconductor substrate along side of the gate electrode in the memory cell region and second contact holes exposing a portion of the capping pattern in the peripheral circuit region such that a bottom surface of the second contact hole is spaced apart from a top surface of the gate conductive pattern. A first plug conductive layer is filled in the first contact holes and a second plug conductive layer is filled in the second contact holes. A planarizing process is performed to expose the capping patterns such that first contact plugs are formed in the memory cell region and second contact plugs are formed in the peripheral circuit region.

摘要翻译： 一种制造半导体器件的方法包括提供包括存储单元区域和外围电路区域的半导体衬底。 包括栅极导电图案和封盖图案的栅电极形成在存储单元区域和外围电路区域上。 形成覆盖栅电极的层间电介质。 图案化层间电介质以形成沿着存储单元区域中的栅极电极的侧面暴露半导体衬底的第一接触孔，以及露出外围电路区域中的封盖图案的一部分的第二接触孔，使得第二接触件的底表面 孔与栅极导电图案的顶表面间隔开。 第一插头导电层填充在第一接触孔中，第二插头导电层填充在第二接触孔中。 执行平面化处理以暴露封盖图案，使得在存储单元区域中形成第一接触插塞，并且在外围电路区域中形成第二接触插塞。

公开(公告)号：US20100131717A1

公开(公告)日：2010-05-27

申请号：US12276072

申请日：2008-11-21

申请人： Dan P. Dumarot ,  Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim ,  Eugene B. Risi

发明人： Dan P. Dumarot ,  Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim ,  Eugene B. Risi

IPC分类号： G06F12/08

CPC分类号： G06F12/0888 ,  G06F11/1666 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1032

摘要： This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

摘要翻译： 本发明描述了一种用于多核处理器的装置，计算机体系结构，存储器结构，存储器控制和高速缓存存储器操作方法。 逻辑内核以低产出或致命性能绕过即时缓存单元。 核心安装（多个）高速缓存单元可能已被其他逻辑内核使用。 所选高速缓存存储单元提供具有相同内容的多个逻辑核。 共享高速缓冲存储器单元为所有安装核心提供缓存搜索，命中，未命中和回写功能。 该方法通过共享可能已经接合其他逻辑核心的高速缓存存储器块来恢复其高速缓冲存储器块不可操作的逻辑核心。 该方法用于提高剩余系统的可靠性和性能。

公开(公告)号：US20100131716A1

公开(公告)日：2010-05-27

申请号：US12275552

申请日：2008-11-21

申请人： Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim

发明人： Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811 ,  G06F11/1666 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0888 ,  G06F2212/1032

摘要： This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

摘要翻译： 本发明描述了一种用于多核处理器的装置，计算机体系结构，存储器结构，存储器控制和高速缓存存储器操作方法。 当面对具有低产量或致命性能的即时高速缓冲存储器单元时，逻辑核心共享请求。 核心安装（多个）高速缓存单元可能已被其他逻辑内核使用。 所选高速缓存存储单元提供具有相同内容的多个逻辑核。 共享高速缓冲存储器单元为所有安装核心提供缓存搜索，命中，未命中和回写功能。 该方法通过共享可能已经接合其他逻辑核心的高速缓存存储器块来恢复其高速缓冲存储器块不可操作的逻辑核心。 该方法用于提高剩余系统的可靠性和性能。

公开(公告)号：US20100066496A1

公开(公告)日：2010-03-18

申请号：US12210371

申请日：2008-09-15

申请人： Choongyeun CHO ,  Richard FERRI ,  Daeik KIM ,  Jonghae KIM ,  Moon Ju KIM

发明人： Choongyeun CHO ,  Richard FERRI ,  Daeik KIM ,  Jonghae KIM ,  Moon Ju KIM

IPC分类号： H04Q5/22

CPC分类号： H04Q9/00 ,  H04Q2209/47

摘要： An identification method and identification device are presented employing radio frequency and acoustic wave communication modes. The identification method includes: receiving at an acoustic wave and radio frequency identification device an acoustic wave signal of a first frequency and a radio frequency signal of a second frequency, where the acoustic wave signal and the radio frequency signal are received from an acoustic wave and radio frequency identification reader, and the first frequency and the second frequency are different frequencies; and responding to the receiving by transmitting at least one of an acoustic wave identification (AWID) or a radio frequency identification (RFID) from the acoustic wave and radio frequency identification device.

摘要翻译： 采用射频和声波通信方式提出了识别方法和识别装置。 识别方法包括：在声波和射频识别装置处接收第一频率的声波信号和从声波接收声波信号和射频信号的第二频率的射频信号， 射频识别读取器，第一频率和第二频率是不同的频率; 以及通过从声波和射频识别装置发送声波识别（AWID）或射频识别（RFID）中的至少一个来响应于接收。