公开(公告)号：US20140246782A1

公开(公告)日：2014-09-04

申请号：US14141947

申请日：2013-12-27

申请人： Jiyoung KIM ,  Daeik KIM ,  Kang-Uk KIM ,  Nara KIM ,  Jemin PARK ,  Kyuhyun LEE ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  HyeongSun HONG ,  Yoosang HWANG

发明人： Jiyoung KIM ,  Daeik KIM ,  Kang-Uk KIM ,  Nara KIM ,  Jemin PARK ,  Kyuhyun LEE ,  Hyun-Woo CHUNG ,  Gyoyoung JIN ,  HyeongSun HONG ,  Yoosang HWANG

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/10897 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact.

摘要翻译： 一种制造半导体器件的方法包括提供具有第一表面和与第一表面相对的第二表面的半导体衬底，形成对准键和穿过半导体衬底的一部分并从第一表面延伸到第二表面的连接触点 在所述半导体衬底的所述第一表面上形成第一电路，使得所述第一电路电连接到所述连接触点，使所述半导体衬底的所述第二表面凹陷以形成暴露所述对准键和所述连接触点的第三表面，以及 在半导体衬底的第三表面上形成第二电路，使得第二电路电连接到连接触点。

公开(公告)号：US20140203357A1

公开(公告)日：2014-07-24

申请号：US14162859

申请日：2014-01-24

申请人： Daeik KIM ,  Jiyoung KIM ,  Jemin PARK ,  Nakjin SON ,  Yoosang HWANG

发明人： Daeik KIM ,  Jiyoung KIM ,  Jemin PARK ,  Nakjin SON ,  Yoosang HWANG

IPC分类号： H01L29/423 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L21/26586 ,  H01L21/823437 ,  H01L29/7827 ,  H01L29/7831

摘要： According to a method of manufacturing a semiconductor device, hard mask lines are formed in parallel in a substrate and the substrate between the hard mask lines is etched to form grooves. A portion of the hard mask line and a portion of the substrate between the grooves are etched. A top surface of the etched portion of the substrate between the grooves is higher than a bottom surface of the groove. A conductive layer is formed to fill the grooves. The conductive layer is etched to form conductive patterns in the grooves, respectively.

摘要翻译： 根据半导体装置的制造方法，在基板上平行地形成硬掩模线，并且蚀刻硬掩模线之间的基板以形成凹槽。 硬掩模线的一部分和凹槽之间的基板的一部分被蚀刻。 在槽之间的衬底的蚀刻部分的顶表面高于槽的底表面。 形成导电层以填充凹槽。 蚀刻导电层以分别在凹槽中形成导电图案。

公开(公告)号：US20140112050A1

公开(公告)日：2014-04-24

申请号：US14051841

申请日：2013-10-11

申请人： Jemin PARK

发明人： Jemin PARK

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

摘要： A semiconductor device includes a plurality of word lines; a plurality of bit lines; and a plurality of bit line node contacts. The plurality of word lines extend in a first direction in or on a substrate. The plurality of bit lines crosses over the plurality of word lines. Each of the plurality of bit line node contacts connects a corresponding bit line to the substrate, and each of the plurality of bit line node contacts has a width substantially equal to a width of the corresponding bit line.

摘要翻译： 半导体器件包括多个字线; 多个位线; 和多个位线节点接点。 多个字线在衬底中或衬底上沿第一方向延伸。 多个位线在多个字线上交叉。 多个位线节点触点中的每一个将对应的位线连接到衬底，并且多个位线节点触点中的每一个具有基本上等于对应位线的宽度的宽度。