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    PROGRAMMABLE ELECTRO-MAGNETIC-INTERFERENCE (EMI) REDUCTION WITH ENHANCED NOISE IMMUNITY AND PROCESS TOLERANCE
    1.
    发明申请
    PROGRAMMABLE ELECTRO-MAGNETIC-INTERFERENCE (EMI) REDUCTION WITH ENHANCED NOISE IMMUNITY AND PROCESS TOLERANCE 有权
    可编程电磁干扰（EMI）减少与增强的噪声免疫和过程公差

    公开(公告)号：US20120126901A1

    公开(公告)日：2012-05-24

    申请号：US12948896

    申请日：2010-11-18

    申请人： Chi Tak (Gerry) LEUNG ,  Chik Wai (David) NG ,  Hing Kit KWAN ,  Wai Kit (Victor) SO ,  Po Wah CHANG ,  Wing Cheong MAK ,  Kwok Kuen KWONG

    发明人： Chi Tak (Gerry) LEUNG ,  Chik Wai (David) NG ,  Hing Kit KWAN ,  Wai Kit (Victor) SO ,  Po Wah CHANG ,  Wing Cheong MAK ,  Kwok Kuen KWONG

    IPC分类号： H03L7/00

    CPC分类号： H03L7/08

    摘要： A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.

    摘要翻译： 频率抖动电路通过扩展时钟的频谱来减少引起电磁干扰（EMI）的辐射。 该时钟是将数字计数值驱动到数模转换器（DAC）的计数器。 DAC输出宽电压摆幅的锯齿波。 减法器缩小电压摆幅，产生用作上限电压的减小摆动锯齿波。 当电流泵对电容器充电和放电超过电压限制时，比较器触发设置复位锁存器来切换时钟。 由于上限电压是来自减法器的减少的锯齿波，所以对电容器充电的时间量变化，使时钟的周期抖动。 可以通过对减法器中的反馈电阻进行编程来调整抖动度。 减法器可降低抖动对DAC误差的灵敏度，从而实现廉价，精度更低的DAC。

    ESD Protection using a Capacitivly-Coupled Clamp for Protecting Low-Voltage Core Transistors from High-Voltage Outputs
    2.
    发明申请
    ESD Protection using a Capacitivly-Coupled Clamp for Protecting Low-Voltage Core Transistors from High-Voltage Outputs 有权
    使用电容耦合钳位保护低压芯片晶体管的ESD保护从高压输出

    公开(公告)号：US20100315748A1

    公开(公告)日：2010-12-16

    申请号：US12481696

    申请日：2009-06-10

    申请人： Kwok Kuen Kwong ,  Chik Wai Ng ,  Wai Kit (Victor) SO ,  Hing Kit KWAN

    发明人： Kwok Kuen Kwong ,  Chik Wai Ng ,  Wai Kit (Victor) SO ,  Hing Kit KWAN

    IPC分类号： H02H9/00

    CPC分类号： H03K19/00315 ,  H01L27/0266 ,  H03K19/018557

    摘要： An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.

    摘要翻译： 静电放电（ESD）保护电路保护核心晶体管。 n沟道输出晶体管的栅极的内部节点连接到n沟道栅极 - 接地晶体管的漏极到地。 栅极接地晶体管的栅极是通过ESD耦合电容器耦合到输出并由n沟道禁用晶体管和漏电阻器接地的耦合栅极节点。 n沟道禁用晶体管的栅极连接电源，并在供电时禁用ESD保护电路。 施加到输出端的ESD脉冲通过ESD耦合电容器耦合，使耦合栅极节点高电压，并接通栅极 - 接地晶体管，使n沟道输出晶体管的栅极接地，从而分解ESD电流。 防止ESD脉冲通过栅极接地晶体管的n沟道输出晶体管的寄生米勒电容器耦合。

    FUSE CELL AND METHOD FOR PROGRAMMING THE SAME
    4.
    发明申请
    FUSE CELL AND METHOD FOR PROGRAMMING THE SAME 有权
    保险丝盒及其编程方法

    公开(公告)号：US20090045867A1

    公开(公告)日：2009-02-19

    申请号：US11838051

    申请日：2007-08-13

    申请人： David Kwok Kuen Kwong ,  Ho Ming Karen Wan ,  Kam Chuen Wan ,  Chik Wai Ng

    发明人： David Kwok Kuen Kwong ,  Ho Ming Karen Wan ,  Kam Chuen Wan ,  Chik Wai Ng

    IPC分类号： H01H85/00

    CPC分类号： G11C17/16 ,  Y02P80/30

    摘要： The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.

    摘要翻译： 用于当前要求保护的发明的熔丝单元结构371采用多个熔丝结构301,302代替单个熔丝结构。 因此，耦合到其它片上器件的这些熔丝结构的端子在编程电压施加到熔丝焊盘311时始终处于地电位。由于以下事实，该方法克服了先前的单熔丝问题，这是因为足够高的编程 可以施加电压来熔断具有意想不到的高电阻的熔丝结构，而不会损坏附近的片上器件。 此外，即使保险丝结构301,302中的一个具有在典型条件下不会被烧断的异常高电阻，由于熔丝单元371中的另一熔丝结构的吹动，仍然可以实现期望的电路修整结果。

    Constant-Current Control Module using Inverter Filter Multiplier for Off-line Current-Mode Primary-Side Sense Isolated Flyback Converter
    6.
    发明申请
    Constant-Current Control Module using Inverter Filter Multiplier for Off-line Current-Mode Primary-Side Sense Isolated Flyback Converter 有权
    恒流控制模块使用变频滤波乘法器进行离线电流模式初级侧检测隔离反激式转换器

    公开(公告)号：US20110216559A1

    公开(公告)日：2011-09-08

    申请号：US12718707

    申请日：2010-03-05

    申请人： Chik Wai (David) Ng ,  Hing Kit Kwan ,  Po Wah Chang ,  Wai Kit (Victor) So ,  Kwok Kuen Kwong

    发明人： Chik Wai (David) Ng ,  Hing Kit Kwan ,  Po Wah Chang ,  Wai Kit (Victor) So ,  Kwok Kuen Kwong

    IPC分类号： H02M3/335

    CPC分类号： H02M3/335

    摘要： A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control.

    摘要翻译： 回扫AC-DC电力转换器具有恒定电流控制回路，其感测变压器中的主要输出电流，以在没有昂贵的光隔离器的情况下控制次级输出。 初级侧控制电路可以使用准谐振（QR）或脉冲宽度调制（PWM）控制回路来切换通过变压器的一次电流的开和关。 将反馈电压与从初级电流回路感测的初级侧电压进行比较，以打开和关闭开关。 乘法器环路使用乘法器产生反馈电压。 电平移位反相器和低通滤波器通过将开关的占空比乘以反馈电压作为乘法器，以产生滤波电压。 高增益误差放大器将滤波电压与参考电压进行比较，以产生反馈电压。 乘法器产生二次电流和参考电压之间的简单关系，产生简化的电流控制。

    Gain control circuit
    8.
    发明授权
    Gain control circuit 有权
    增益控制电路

    公开(公告)号：US07659780B2

    公开(公告)日：2010-02-09

    申请号：US11947085

    申请日：2007-11-29

    申请人： Chit Ah Mak ,  Chun Fai Wong ,  Lap Chi Leung ,  Xiaofei Kuang ,  Jennifer Shuet Yan Ho ,  David Kwok Kuen Kwong

    发明人： Chit Ah Mak ,  Chun Fai Wong ,  Lap Chi Leung ,  Xiaofei Kuang ,  Jennifer Shuet Yan Ho ,  David Kwok Kuen Kwong

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45475 ,  H03F1/3211 ,  H03F1/486 ,  H03F1/56 ,  H03F3/45192 ,  H03F2200/36 ,  H03F2200/513 ,  H03F2203/45138 ,  H03F2203/45356 ,  H03G1/0023 ,  H03G7/004 ,  H03G7/06

    摘要： A gain control circuit including a resistor with a first terminal and a second terminal; an operational amplifier with an inverting terminal thereof electrically coupled to said first terminal of said resistor; a non-inverting terminal thereof; and an output terminal thereof; an amplifier circuit for transforming the voltage change of said operational amplifier output into a substantially exponential current change; wherein the output of said amplifier circuit is electrically coupled to said inverting terminal of said operational amplifier. The above described gain control circuit is able to perform wide bandwidth input signal buffering with linearity under low voltage and low power conditions. The circuit also offers low output impedances without the need of additional buffers and hence minimizing circuit size and manufacturing costs.

    摘要翻译： 一种增益控制电路，包括具有第一端子和第二端子的电阻器; 运算放大器，其反相端电耦合到所述电阻器的所述第一端子; 其非反相端子; 及其输出端子; 放大器电路，用于将所述运算放大器输出的电压变化变换成基本指数的电流变化; 其中所述放大器电路的输出电耦合到所述运算放大器的所述反相端。 上述增益控制电路能够在低电压和低功率条件下以线性度执行宽带宽输入信号缓冲。 该电路还提供低输出阻抗，而不需要额外的缓冲器，因此最小化电路尺寸和制造成本。

    Feedback controller having multiple feedback paths
    9.
    发明申请
    Feedback controller having multiple feedback paths 有权
    反馈控制器具有多个反馈路径

    公开(公告)号：US20080238396A1

    公开(公告)日：2008-10-02

    申请号：US11731167

    申请日：2007-03-30

    申请人： Chik Wai Ng ,  Yat To Wong ,  David Kwok Kuen Kwong

    发明人： Chik Wai Ng ,  Yat To Wong ,  David Kwok Kuen Kwong

    IPC分类号： G05F1/10 ,  H03K5/153

    CPC分类号： H03K7/08 ,  H03F3/217 ,  H03F3/45475

    摘要： A feedback controller comprises first and second feedback circuits. The first feedback circuit is connected between an input node and an output node and has an error node. The first feedback circuit comprising a feedback amplifier for comparing a feedback signal to a reference signal and providing an error signal, and a comparator for comparing the error signal to a second reference signal and providing an output signal. The second feedback circuit is connected between the input node and the error node and comprises a current source coupled to the error node and a controller coupled to the input node for controlling the current source in response to a value of the feedback signal being above or below a threshold value.

    摘要翻译： 反馈控制器包括第一和第二反馈电路。 第一反馈电路连接在输入节点和输出节点之间，并具有错误节点。 第一反馈电路包括用于将反馈信号与参考信号进行比较并提供误差信号的反馈放大器，以及用于将误差信号与第二参考信号进行比较并提供输出信号的比较器。 所述第二反馈电路连接在所述输入节点和所述误差节点之间，并且包括耦合到所述误差节点的电流源和耦合到所述输入节点的控制器，用于响应于所述反馈信号的值高于或低于 一个阈值。

    Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock
    10.
    发明申请
    Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock 有权
    使用电压升压时钟的单功率晶体管电池充电电路

    公开(公告)号：US20110267008A1

    公开(公告)日：2011-11-03

    申请号：US13179107

    申请日：2011-07-08

    申请人： Kwok Kuen Kwong ,  Yat To Wong ,  Ho Ming (Karen) Wan ,  Chik Wai Ng

    发明人： Kwok Kuen Kwong ,  Yat To Wong ,  Ho Ming (Karen) Wan ,  Chik Wai Ng

    IPC分类号： H02J7/00

    CPC分类号： H02J7/0031

    摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.

    摘要翻译： 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极以截止功率晶体管。