公开(公告)号：US20070018248A1

公开(公告)日：2007-01-25

申请号：US11184244

申请日：2005-07-19

申请人： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo ,  Jeffrey Sleight

发明人： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo ,  Jeffrey Sleight

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092

摘要： Disclosed are a multi-threshold CMOS circuit and a method of designing such a circuit. The preferred embodiment combines an MTCMOS scheme and a hybrid SOI-epitaxial CMOS structure. Generally, the logic transistors (both nFET and pFET) are placed in SOI, preferably in a high-performance, high density UTSOI; while the headers or footers are made of bulk epitaxial CMOS devices, with or without an adaptive well-biasing scheme. The logic transistors are based on (100) SOI devices or super HOT, the header devices are in bulk (100) or (110) pFETs with or without an adaptive well biasing scheme, and the footer devices are in bulk (100) NFET with or without an adaptive well biasing scheme.

摘要翻译： 公开了一种多阈值CMOS电路和一种设计这种电路的方法。 优选实施例组合MTCMOS方案和混合SOI外延CMOS结构。 通常，逻辑晶体管（nFET和pFET都）放置在SOI中，优选地以高性能，高密度的UTSOI; 而集管或页脚由大量外延CMOS器件制成，具有或不具有自适应阱偏置方案。 逻辑晶体管基于（100）SOI器件或超级HOT，头部器件处于具有或不具有自适应阱偏置方案的体（100）或（110）pFET中，并且脚踏器件处于本体（100）NFET中 或没有自适应井偏置方案。

公开(公告)号：US20060226493A1

公开(公告)日：2006-10-12

申请号：US11100883

申请日：2005-04-07

申请人： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo

发明人： Ching-Te Chuang ,  Koushik Das ,  Shih-Hsien Lo

IPC分类号： H01L29/94

CPC分类号： H03K19/0016 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance penalty associated with conventional PFET headers. A first embodiment of the invention provides a HOT-B high-VTH thick oxide bulk PFET header scheme. This header scheme can be expanded by application of a positive gate bias VPOS (VPOS>VDD) to the HOT-B PFET header during standby mode and a negative gate bias VNEG (VNEG

摘要翻译： 公开了结合MTCMOS和混合定向技术的CMOS电路设计，以实现高性能和低待机泄漏功率的双重目标。 本发明利用HOT技术中的厚氧化物高VTH PFET集线器的新型组合与各种栅极和体偏置方案，以显着降低与常规PFET集管相关的性能损失。 本发明的第一实施例提供了一种HOT-B高VTH厚氧化物体PFET头方案。 可以通过在待机模式期间将正栅极偏置VPOS（VPOS> VDD）施加到HOT-B PFET头并且在活动模式下使用负栅极偏置VNEG（VNEG

公开(公告)号：US20050040881A1

公开(公告)日：2005-02-24

申请号：US10644211

申请日：2003-08-20

申请人： Richard Brown ,  Ching-Te Chuang ,  Peter Cook ,  Koushik Das ,  Rajiv Joshi

发明人： Richard Brown ,  Ching-Te Chuang ,  Peter Cook ,  Koushik Das ,  Rajiv Joshi

IPC分类号： H03K19/00 ,  H03K3/01

CPC分类号： H03K19/0016

摘要： A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETS) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.

摘要翻译： 具有降低的亚阈值泄漏的多阈值集成电路（IC）和减少泄漏的方法。 电路逻辑电路和电源连接（Vdd和Ground）之间的可选供电开关器件（NFET和/或PFETS）具有比正常电路器件更高的阈值。 当供电开关装置打开时，一些装置可能具有降低的阈值。 具有更高阈值电压和宽度的标题/页脚装置可用于进一步降低电阻和保持/降低电阻。 或者，可以堆叠高阈值装置以进一步将泄漏减少到达到甚至更高阈值所达到的点。 中间电源连接在器件上可能具有去耦电容，器件可以锥形化，以获得最佳堆叠高度和最佳锥度比，以最大限度地减少电路泄漏和电路延迟。

公开(公告)号：US20060232321A1

公开(公告)日：2006-10-19

申请号：US11106913

申请日：2005-04-15

申请人： Ching-Te Chuang ,  Koushik Das ,  Keunwoo Kim

发明人： Ching-Te Chuang ,  Koushik Das ,  Keunwoo Kim

IPC分类号： H03K17/687

CPC分类号： H01L27/105 ,  G11C5/14 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/785 ,  H01L29/78648 ,  H03K3/356156

摘要： A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.

摘要翻译： 具有强大数据保持能力的新型电源门控结构，仅使用一个单栅极器件来提供电源门控开关和虚拟电源/接地二极管钳位功能。 该方案降低了电源门控结构的晶体管数量，面积和电容，从而提高了电路性能，功率和泄漏。 该方案通过基于混合模式物理的二维数值模拟与常规电力门控结构进行比较。 还提出了拟议方案的虚拟供应/地面反弹分析。