公开(公告)号：US06232184B1

公开(公告)日：2001-05-15

申请号：US09394270

申请日：1999-09-10

申请人： Ling-Sung Wang ,  Chingfu Lin

发明人： Ling-Sung Wang ,  Chingfu Lin

IPC分类号： H01L21336

CPC分类号： H01L21/28273

摘要： A method of manufacturing the floating gate of a stacked-gate type of nonvolatile memory unit. A gate oxide layer and a polysilicon layer are sequentially formed over a substrate. The polysilicon layer is etched to form a floating gate above the gate oxide layer. During the polysilicon etching operation, a polymeric material is also deposited on the sidewalls of the floating gate and over the exposed gate oxide. An isotropic chemical dry etching of the floating gate is carried out so that its bottom section is slightly wider than its top section. Finally, a thermal oxidation operation is carried out to form an oxide layer over the floating gate.

摘要翻译： 一种制造堆叠栅极型非易失性存储器单元的浮置栅极的方法。 栅极氧化层和多晶硅层依次形成在衬底上。 蚀刻多晶硅层以在栅极氧化物层上方形成浮置栅极。 在多晶硅蚀刻操作期间，聚合物材料也沉积在浮动栅极的侧壁上以及暴露的栅极氧化物上。 执行浮动栅极的各向同性化学干蚀刻，使其底部部分比其顶部部分稍宽。 最后，进行热氧化操作以在浮栅上形成氧化物层。

公开(公告)号：US6162679A

公开(公告)日：2000-12-19

申请号：US306261

申请日：1999-05-06

申请人： Chingfu Lin

发明人： Chingfu Lin

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522

CPC分类号： H01L28/91 ,  H01L21/32136 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/1085 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming trench type DRAM capacitor. An insulation layer is formed on a substrate with a trench exposing a conductive region of the substrate. A first conductive layer is formed and conformal to a surface profile of the substrate. A photoresist layer is formed over the first conductive layer to fill the trench. A three-stage of etching process is carried out. A first stage of etching step is carried out to remove a portion of the photoresist layer, thereby exposing the first conductive layer. A second stage step is carried out to remove the first conductive layer by performing an isotropic dry etching step. The first conductive layer is slightly over-etched so that a portion of the first conductive layer inside the trench is also removed. Therefore, the first conductive layer inside the trench will be at a distance lower than a top surface of the insulation layer. A third stage of etching operation is carried out to remove the remaining photoresist layer so that the remaining first conductive layer inside the trench is exposed. A dielectric layer and a second conductive layer are sequentially formed over the first conductive layer.

摘要翻译： 一种形成沟槽型DRAM电容器的方法。 在具有暴露衬底的导电区域的沟槽的衬底上形成绝缘层。 形成第一导电层并与衬底的表面轮廓共形。 在第一导电层上形成光致抗蚀剂层以填充沟槽。 进行三级蚀刻工艺。 执行蚀刻步骤的第一阶段以去除光致抗蚀剂层的一部分，从而暴露出第一导电层。 通过进行各向同性的干蚀刻工序，进行第二阶段的工序来除去第一导电层。 第一导电层略微过蚀刻，使得沟槽内部的第一导电层的一部分也被去除。 因此，沟槽内的第一导电层将处于比绝缘层的顶表面低的距离处。 执行蚀刻操作的第三阶段以去除剩余的光致抗蚀剂层，使得沟槽内剩余的第一导电层被暴露。 电介质层和第二导电层依次形成在第一导电层的上方。

公开(公告)号：US07273808B1

公开(公告)日：2007-09-25

申请号：US10356960

申请日：2003-02-03

申请人： Chingfu Lin

发明人： Chingfu Lin

IPC分类号： H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making a multilayer interconnect electronic component structure, and, in particular, an integrated circuit semiconductor device made using a copper damascene method is provided. The process of the invention uses a method for pre-cleaning exposed copper surfaces in the structure. The method employs a cleaning composition containing a nitrogen containing material and an oxygen containing material and also optionally a hydrogen containing material to remove the copper oxide film on copper surfaces in the structure. The preferred nitrogen material is nitrogen gas and the preferred oxygen material is oxygen gas. The gas mixture is preferably energized to form a plasma which is used to contact and remove the copper oxide and clean the structure. A two-step process may be used employing a nitrogen/oxygen mixture and then a hydrogen containing gas mixture such as Ar/H2. It has also been found that the advantages of the method include not only removal of residue and copper oxide from the structure without significant dielectric shift of the dielectric, but also provides enhanced metal adhesion to the treated dielectric as well as surface passivation of the dielectric.

摘要翻译： 提供一种制造多层互连电子部件结构的方法，特别是使用铜镶嵌方法制成的集成电路半导体器件。 本发明的方法使用预清洗结构中暴露的铜表面的方法。 该方法采用包含含氮材料和含氧材料的清洁组合物，并且还可选地使用含氢材料以除去该结构中铜表面上的氧化铜膜。 优选的氮气是氮气，优选的氧气是氧气。 气体混合物优选被通电以形成用于接触和去除氧化铜并清洁结构的等离子体。 可以使用氮/氧混合物，然后使用含氢气体混合物如Ar / H 2 N 2的两步法。 还已经发现，该方法的优点不仅包括从结构中去除残留物和氧化铜而没有电介质的显着的介电偏移，而且还提供增强的金属对于经处理的电介质的粘附以及电介质的表面钝化。

公开(公告)号：US06261921B1

公开(公告)日：2001-07-17

申请号：US09395110

申请日：1999-09-14

申请人： Ching-Lang Yen ,  Chingfu Lin

发明人： Ching-Lang Yen ,  Chingfu Lin

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A method of forming a shallow trench isolation structure is described. A mask layer and a photoresist layer with an opening are formed on a substrate in sequence. The photoresist layer serves as an etching mask, and then a portion of the mask layer and a portion of the substrate are etched to form a trench in the substrate. A portion of the photoresist layer is removed, and the opening is in-situ widened. Then, a portion of the mask layer exposed by the widened opening is removed. In addition, a top corner of the trench is rounded after removing the portion of the mask layer. Finally, the trench is filled with an insulation material to form a shallow trench isolation structure.

摘要翻译： 描述形成浅沟槽隔离结构的方法。 依次在基板上形成具有开口的掩模层和光致抗蚀剂层。 光致抗蚀剂层用作蚀刻掩模，然后蚀刻掩模层的一部分和衬底的一部分以在衬底中形成沟槽。 去除光致抗蚀剂层的一部分，并且原位加宽开口。 然后，去除由加宽的开口露出的掩模层的一部分。 此外，在去除掩模层的部分之后，沟槽的顶角是圆形的。 最后，沟槽填充绝缘材料以形成浅沟槽隔离结构。

公开(公告)号：US06350681B1

公开(公告)日：2002-02-26

申请号：US09780549

申请日：2001-02-09

申请人： Anseime Chen ,  Chingfu Lin ,  Yi-Fang Cheng ,  I-Hsiung Huang

发明人： Anseime Chen ,  Chingfu Lin ,  Yi-Fang Cheng ,  I-Hsiung Huang

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a multiple layer damascene structure. A substrate comprising of a multi-layered stack that includes, from bottom to top, a metallic layer, a first etching stop layer, a first dielectric layer, a second etching stop layer and a second dielectric layer is provided. A photoresist layer having large area openings and vias pattern is formed over the substrate. Large area openings and vias that expose a portion of the first etching stop layer are formed in the substrate. A barrier layer that fills all the large area openings and vias is formed over the substrate. Chemical-mechanical polishing is conducted to remove a portion of the barrier layer and expose the second dielectric layer. A second photoresist having a trench pattern thereon is formed over the substrate. Using the second photoresist as a mask, etching is conducted so that the second etching stop layer around the vias is exposed. Lastly, the barrier layer is removed.

摘要翻译： 一种形成多层镶嵌结构的方法。 提供一种包括多层叠层的衬底，其包括从底部到顶部的金属层，第一蚀刻停止层，第一介电层，第二蚀刻停止层和第二介电层。 在衬底上形成具有大面积开口和通孔图案的光致抗蚀剂层。 在基板上形成露出一部分第一蚀刻停止层的大面积开口和通孔。 填充所有大面积开口和通孔的阻挡层形成在衬底上。 进行化学机械抛光以去除阻挡层的一部分并暴露第二介电层。 其上具有沟槽图案的第二光致抗蚀剂形成在衬底上。 使用第二光致抗蚀剂作为掩模，进行蚀刻，使得通孔周围的第二蚀刻停止层露出。 最后，去除阻挡层。

公开(公告)号：US06277742B1

公开(公告)日：2001-08-21

申请号：US09342570

申请日：1999-06-29

申请人： Chien-Jung Wang ,  Chingfu Lin ,  Lien-Jung Hung

发明人： Chien-Jung Wang ,  Chingfu Lin ,  Lien-Jung Hung

IPC分类号： H01L2144

CPC分类号： H01L21/02071 ,  H01L21/32136 ,  H01L21/76838 ,  Y10S438/906

摘要： A method of protecting a tungsten plug from corroding. After a tungsten plug is formed in a substrate, a wire is formed on the substrate to couple with the tungsten plug. The substrate is dipped into an electrolyte solution. The electrolyte solution is acid or alkaline enough to discharge charges accumulated on the wire. Then, a wet cleaning process is performed to remove polymer formed on the wire.

摘要翻译： 防止钨丝塞腐蚀的方法。 在基板中形成钨插塞之后，在基板上形成导线以与钨插塞耦合。 将基板浸入电解质溶液中。 电解质溶液是酸性或碱性足以释放积累在电线上的电荷。 然后，进行湿式清洗处理以除去在导线上形成的聚合物。

公开(公告)号：US06277741B1

公开(公告)日：2001-08-21

申请号：US09282052

申请日：1999-03-29

申请人： Chingfu Lin

发明人： Chingfu Lin

IPC分类号： H01L2144

CPC分类号： H01L21/32137 ,  H01L21/32115 ,  H01L21/7684

摘要： A method for planarizing a polysilicon layer is described. A polysilicon layer is etched with an oxygen-based gas and a halogen-based gas. The oxygen-based gas comprises an nitrogen oxide oxygen gas. The nitrogen oxide gas includes NO, NO2, N2O, or the combination thereof. The halogen-based gas includes a F, Cl, Br., I, NF3, SF6, Cl2, HCl, SiCl4, fluorocarbon, or a combination thereof. The fluorocarbon includes CF4, CHF3, CH2F2, CH3F, or the like.

摘要翻译： 描述了一种用于平坦化多晶硅层的方法。 用氧基气体和卤素气体蚀刻多晶硅层。 氧基气体包含氮氧化物氧气。 氮氧化物气体包括NO，NO 2，N 2 O或其组合。 卤素类气体包括F，Cl，Br，I，NF 3，SF 6，Cl 2，HCl，SiCl 4，碳氟化合物或其组合。 氟碳化合物包括CF 4，CHF 3，CH 2 F 2，CH 3 F等。

公开(公告)号：US20050085069A1

公开(公告)日：2005-04-21

申请号：US09863647

申请日：2001-05-23

申请人： Chingfu Lin ,  Hsueh-Chung Chen

发明人： Chingfu Lin ,  Hsueh-Chung Chen

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76808

摘要： A substrate having a conductive layer is provided. A dielectric layer is then formed above the conductive layer. At least one via hole is then formed in the dielectric layer, to expose a portion of the conductive layer. The conductive layer is then covered with a gap fill polymer layer, to completely fill the via hole. A chemical mechanical polishing step is performed to remove the partial gap fill polymer layer on the outside of the via hole. An etching step, is performed to remove a portion of partial gap fill polymer layer remaining in the via hole, resulting in a partial gap fill polymer. A lithographic process is conducted to form a patterned photoresist layer over the dielectric layer. The photoresist layer has an opening that exposes the via hole and partial gap fill polymer. A portion of the dielectric layer exposed by the opening is etched away, to form a trench in the dielectric layer. The photoresist layer and the partial fill polymer layer are then removed, to expose a part of the conductive layer. The via hole and trench are filled with metal material, to form a plug and line simultaneously.

摘要翻译： 提供具有导电层的基板。 然后在导电层上方形成电介质层。 然后在电介质层中形成至少一个通孔，以暴露导电层的一部分。 然后用间隙填充聚合物层覆盖导电层，以完全填充通孔。 执行化学机械抛光步骤以去除通孔外部的部分间隙填充聚合物层。 执行蚀刻步骤以去除残留在通孔中的部分间隙填充聚合物层的一部分，导致部分间隙填充聚合物。 进行光刻工艺以在电介质层上形成图案化的光致抗蚀剂层。 光致抗蚀剂层具有露出通孔和部分间隙填充聚合物的开口。 通过开口暴露的电介质层的一部分被蚀刻掉，以在电介质层中形成沟槽。 然后去除光致抗蚀剂层和部分填充聚合物层，以暴露导电层的一部分。 通孔和沟槽用金属材料填充，同时形成插头和线。

公开(公告)号：US06221734B1

公开(公告)日：2001-04-24

申请号：US09354622

申请日：1999-07-15

申请人： Chingfu Lin

发明人： Chingfu Lin

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A method of reducing a chemical mechanical polishing (CMP) dishing effect. A plurality of trenches are formed in the substrate, while a first insulating layer, such as silicon oxide layer is formed on the substrate to fill those trenches. A chemical reaction, such as nitridation reaction, is performed on the surface of the insulating layer to form a second insulating layer, which is harder than the first insulating layer. CMP is then performed.

摘要翻译： 减少化学机械抛光（CMP）凹陷效应的方法。 在衬底中形成多个沟槽，同时在衬底上形成诸如氧化硅层的第一绝缘层以填充这些沟槽。 在绝缘层的表面上进行氮化反应等化学反应，形成比第一绝缘层硬的第二绝缘层。 然后执行CMP。

公开(公告)号：US6159843A

公开(公告)日：2000-12-12

申请号：US328981

申请日：1999-06-09

申请人： Chingfu Lin

发明人： Chingfu Lin

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/44

CPC分类号： H01L27/10888 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/76897

摘要： A method of fabricating a landing pad. A gate electrode is formed on a substrate. The gate electrode has a top surface covered by a cap layer and a sidewall covered by a spacer. A polysilicon layer is formed to cover the gate. Using an oxygen based etchant to performed an isotropic chemical dry etching on the polysilicon layer, the polysilicon layer is planarized until a part of the spacer is exposed. The polysilicon layer is patterned to form a landing pad in contact with the substrate.

摘要翻译： 一种制造着陆垫的方法。 在基板上形成栅电极。 栅电极具有由盖层覆盖的顶表面和被间隔件覆盖的侧壁。 形成多晶硅层以覆盖栅极。 使用氧基蚀刻剂在多晶硅层上进行各向同性化学干蚀刻，将多晶硅层平坦化直到间隔物的一部分露出。 图案化多晶硅层以形成与衬底接触的着陆焊盘。