公开(公告)号：US5866493A

公开(公告)日：1999-02-02

申请号：US903655

申请日：1997-07-31

Applicant: In Gyu Lee ,  Chong Kwang Yoon ,  Seung Moo Heo ,  Se Hong Chang ,  Jung Ju Kim

Inventor： In Gyu Lee ,  Chong Kwang Yoon ,  Seung Moo Heo ,  Se Hong Chang ,  Jung Ju Kim

IPC: C04B35/457

CPC classification number: C04B35/457

Abstract: According to the method, an aqueous salt solution containing either tin, indium or both, are mixed with an alkali to produce a slurry containing precipitated particles. Then, the slurry is maintained at a predetermined temperature range for a time sufficient to convert the precipitated particles to larger size particles by coagulation or agglomeration. The resulting slurry is then dried and calcined to produce a mixed power. The mixed power is ball milled, press molded and/or cold isostatic press (CIP) molded. The molded body is then sintered to form an ITO sintered body. The ITO sintered body obtained by this process offers superior sinterability whose theoretical density can reach more than 95%.

Abstract translation: 根据该方法，将含有锡，铟或两者的盐水溶液与碱混合以产生含有沉淀颗粒的浆料。 然后，将浆料保持在预定温度范围足以通过凝结或凝聚将沉淀的颗粒转化成更大尺寸的颗粒。 然后将所得浆液干燥并煅烧以产生混合动力。 混合动力是球磨，压模和/或冷等静压（CIP）成型。 然后将成型体烧结以形成ITO烧结体。 通过该方法获得的ITO烧结体提供了优异的烧结性，其理论密度可以达到95％以上。

公开(公告)号：US06320249B1

公开(公告)日：2001-11-20

申请号：US09451450

申请日：1999-11-30

Applicant: Chong Kwang Yoon

Inventor： Chong Kwang Yoon

IPC: H05K702

CPC classification number: H05K3/3436 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/023 ,  H05K1/145 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K2201/049 ,  H05K2201/10045 ,  H05K2201/10378 ,  H05K2201/10719 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multiple line grid (MLG) for use in a multiple line grid array(MLGA) packaging incorporates therein circuit elements, e.g., metal lines, resistors, capacitors, inductors, transistors or combinations thereof, with a view to reducing a size of a printed circuit board on which it is mounted. The MLGA package includes a semifinished package including a surface with a first metal pattern formed thereon for connecting a number of input/output terminals, a printed circuit board(PCB) including a top surface with a second metal pattern formed thereon according to the first metal pattern; and at least of a MLG which is disposed between the semifinished package and the PCB. The MLG includes a non-conductive body incorporated therein a plurality of circuit elements and multiple number of conductors in the form of a column. Each of the conductors is electrically isolated from each other and is electrically connected to the first and the second metal patterns.

Abstract translation: 用于多线栅格阵列（MLGA）封装的多线栅格（MLG）在其中集成了电路元件，例如金属线，电阻器，电容器，电感器，晶体管或其组合，以减少打印的尺寸 其上安装有电路板。 MLGA封装包括半成品封装，其包括其上形成有第一金属图案的表面，用于连接多个输入/输出端子;印刷电路板（PCB），其包括根据第一金属形成在其上的第二金属图案的顶表面 模式; 以及至少设置在半成品封装和PCB之间的MLG。 MLG包括非导电体，其中结合有多个电路元件和多个呈列形式的导体。 每个导体彼此电隔离并且电连接到第一和第二金属图案。

公开(公告)号：US06384477B2

公开(公告)日：2002-05-07

申请号：US09203196

申请日：1998-11-30

Applicant: Chong Kwang Yoon ,  Chan Keun Kim

Inventor： Chong Kwang Yoon ,  Chan Keun Kim

IPC: H01L2349

CPC classification number: H05K3/3426 ,  H01L23/49811 ,  H01L2924/0002 ,  Y02P70/613 ,  H01L2924/00

Abstract: A multiple line grid array package comprising a package body having a first surface and a second surface opposite to the first surface; a first pattern formed on the first surface of the package body and including a number of input/output nodes; a second pattern formed on the second surface of the package body; and a multiple line grid having a nonconductive grid body and a number of conductors formed parallel to a longitudinal axis of the nonconductive grid body on the outer peripheral portion and/or within an inner portion of the multiple line grid and bonded to the package body; wherein each of the conductors is electrically isolated from each other and matches the corresponding one of the number of input/output nodes of the first pattern. A number of such multiple line grids are arranged in a grid pattern to form the multiple line grid array.

Abstract translation: 一种多线栅格阵列封装，包括具有第一表面和与第一表面相对的第二表面的封装体; 形成在包装体的第一表面上并包括多个输入/输出节点的第一图案; 形成在所述封装主体的第二表面上的第二图案; 以及多线栅格，其具有非导电栅格体和多个平行于所述非导电栅格体的纵向轴线的导体，所述多个导体在所述外部周边部分上和/或所述多条线栅格的内部部分内并结合到所述封装主体; 其中每个导体彼此电隔离并且匹配第一图案的输入/输出节点数量中的相应一个。 多个这样的多行网格被排列成网格图案以形成多行网格阵列。