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1.发明公开公开(公告)号：US20240021662A1
公开(公告)日：2024-01-18
申请号：US18473288
申请日：2023-09-25
发明人： Rongbin HU , Can ZHU , Jianan WANG , Guangbing CHEN , Dongbing FU , Zhengping ZHANG , Zhou YU , Zhimei YANG , Min GONG
摘要： The present disclosure provides a polysilicon resistor, a method for manufacturing the same, and a successive approximation register analog-to-digital converter. A polysilicon resistor includes a first silicon substrate; a first silicon oxide layer disposed on the first silicon substrate; a second silicon substrate disposed on the first silicon oxide layer, wherein an insulating isolation structure extends through the second silicon substrate and divides the second silicon substrate into a plurality of substrate isolation areas separated from each other; a second silicon oxide layer disposed on the second silicon substrate; and a polysilicon resistor layer disposed on the second silicon oxide layer, wherein the polysilicon resistor layer includes a plurality of polysilicon resistor blocks separated from each other, the plurality of polysilicon resistor blocks is arranged in one-to-one correspondence with the plurality of substrate isolation areas, and the plurality of polysilicon resistor blocks are connected in series.
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公开(公告)号：US20240223203A1
公开(公告)日：2024-07-04
申请号：US18603189
申请日：2024-03-12
发明人： Yizhou WANG , Lu LIU , Daiguo XU , Can ZHU , Hequan JIANG , Ruzhang LI , Jianan WANG , Guangbing CHEN , Dongbing FU , Zhou YU , Zhengping ZHANG
IPC分类号： H03M1/12
CPC分类号： H03M1/121 , H03M1/1245
摘要： A circuit for channel randomization based on time-interleaved ADC includes: a channel selection module for outputting M clock reception control signals and encoded N data reception control signals based on a main clock and a generated random number; a multi-phase clock distribution module for generating N multi-phase clocks according to a sampling main clock, redistributing the multi-phase clocks according to the clock reception control signals, and outputting M redistributed clock signals; a time-interleaved ADC module for outputting M output data and a corresponding number of channel quantization completion signals according to the redistributed clock signals; an adjustable delay module for setting a delay length for the data reception control signals; and a timing distribution control module for controlling, according to delayed data reception control signals and the channel quantization completion signals, the output data to be output sequentially in chronological order.
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3.发明公开公开(公告)号：US20240281015A1
公开(公告)日：2024-08-22
申请号：US18650065
申请日：2024-04-29
发明人： Yizhou WANG , Lu LIU , Daiguo XU , Can ZHU , Hequan JIANG , Ruzhang LI , Jianan WANG , Guangbing CHEN , Dongbing FU , Zhou YU , Zhengping ZHANG
摘要： An adaptive current generation circuit includes an inverter drive chain, a frequency divider, a frequency detector, a low-pass filter, a static comparator group, and a controllable current mirror. An input analog signal of the input buffer is converted into a frequency discrimination voltage in a direct current form sequentially through conversion of the inverter drive chain, frequency division of the frequency divider, frequency detection of the frequency detector, and conversion of the low-pass filter. Then the static comparator group performs a plurality of times of comparison to obtain N bits of digital codes. Finally, the controllable current mirror is controlled by using the N bits of digital codes. The controllable current mirror provides a magnitude-adjustable input current for the input buffer under control of the N bits of digital codes. A magnitude of the input current is positively correlated with a frequency of the input analog signal.
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公开(公告)号：US20240219944A1
公开(公告)日：2024-07-04
申请号：US18603155
申请日：2024-03-12
发明人： Rongbin HU , Can ZHU , Jianan WANG , Guangbing CHEN , Dongbing FU , Zhengping ZHANG , Zhou YU , Zhimei YANG , Min GONG
摘要： Reference voltage circuits and methods for designing the same are provided. The reference voltage circuit includes: a reference core unit configured to output a reference voltage; a main amplification unit connected to the reference core unit and configured to form feedback to the reference core unit; and a feedforward amplification unit connected to the main amplification unit and configured to form feedforward to the main amplification unit. The reference core unit, the main amplification unit, and the feedforward amplification unit form a third-order negative feedback loop to improve a power supply rejection ratio of the reference voltage.
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公开(公告)号：US20240297660A1
公开(公告)日：2024-09-05
申请号：US18663059
申请日：2024-05-13
发明人： Daiguo XU , Hequan JIANG , Ruzhang LI , Jianan WANG , Dongbing FU , Guangbing CHEN , Zhou YU , Zhengping ZHANG , Can ZHU , Weiqi GAO
IPC分类号： H03M1/44
CPC分类号： H03M1/442
摘要： A comparison method includes: providing a successive approximation register analog-to-digital converter, where the successive approximation register analog-to-digital converter includes n−1 weighted capacitors, a charge transfer capacitor, and a comparator; sampling an differential input signal by using the first weighted capacitor and the charge transfer capacitor; importing the differential input signal stored on the charge transfer capacitor, where the differential input signal is transferred and redistributed on the charge transfer capacitor and n−2 other weighted capacitors than the first weighted capacitor, and completing the first time of comparison; and importing the differential input signal stored on the first weighted capacitor and the differential input signal stored on the charge transfer capacitor, importing a reference voltage by using the second to jth weighted capacitors, where the differential input signal and the reference voltage are transferred and redistributed on a capacitor array, and completing a jth time of comparison.
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公开(公告)号：US20240275370A1
公开(公告)日：2024-08-15
申请号：US18634981
申请日：2024-04-14
发明人： Daiguo XU , Hequan JIANG , Ruzhang LI , Jianan WANG , Dongbing FU , Guangbing CHEN , Zhou YU , Zhengping ZHANG , Can ZHU , Weiqi GAO
CPC分类号： H03K5/2481 , H03M1/08
摘要： A comparator based on a pre-amplifier stage structure and an analog-to-digital converter are provided. The comparator includes: a first pre-amplifier stage, where an input terminal of the first pre-amplifier stage is connected to a differential input signal, to amplify and output the differential input signal so as to output a first differential output signal; a second pre-amplifier stage, where an input terminal of the second pre-amplifier stage is connected to the first differential output signal, to amplify and output the first differential output signal so as to output a second differential output signal, and a positive feedback unit is disposed between an output terminal of the second pre-amplifier stage and the input terminal of the second pre-amplifier stage, to increase a voltage gain of the second pre-amplifier stage by using the positive feedback unit; and a latch, an input terminal thereof connected to the second differential output signal.
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公开(公告)号：US20240120932A1
公开(公告)日：2024-04-11
申请号：US18527355
申请日：2023-12-03
发明人： Yabo NI , Yong ZHANG , Xiaofeng SHEN , Ting LI , Lu LIU , Can ZHU , Jiahao PENG , Liang LI , Dongbing FU , Jianan WANG
CPC分类号： H03M1/164 , H03M1/1038 , H03M1/38
摘要： Embodiments of the disclosure provide a circuit, chip, system, and method for eliminating random perturbation. The circuit includes a weight calculating module for receiving digital signals and random perturbation digital quantity, using least mean square error algorithm to calculate weight deviation iteration coefficient based on digital signal and digital quantity, and updating perturbation weight in real-time according to weight deviation iteration coefficient; and a perturbation eliminating module for eliminating perturbation signal in output digital signal of quantizer according to perturbation weight updated in real-time and updating perturbation weight in real-time according to weight deviation iteration coefficient, and then calculating current perturbation weight in real time to realize self-calibration of perturbation weight. Even if the manufacturing process or working environment of the current chip changes, perturbation weight can be dynamically adjusted, to ideally eliminate perturbation signal in digital signal.
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