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    System and Method for Signaling and Detecting in Wireless Communications Systems
    1.
    发明申请
    System and Method for Signaling and Detecting in Wireless Communications Systems 有权
    无线通信系统中的信令和检测系统与方法

    公开(公告)号：US20120236970A1

    公开(公告)日：2012-09-20

    申请号：US13050437

    申请日：2011-03-17

    申请人： Christian Schlegel ,  Carmela Cozzo

    发明人： Christian Schlegel ,  Carmela Cozzo

    IPC分类号： H04L27/06

    CPC分类号： H04L25/03305

    摘要： A system and method for signaling and detecting in wireless communications systems are provided. A method for processing information includes operating in a first phase, operating in a second phase, and processing the detected information. The first phase includes iteratively inverting a first filtering operation on received signals, and the second phase includes iteratively inverting a second filtering operation on received signals with consideration given to a first estimation error of symbols of the first user and a second estimation error of symbols of the second user.

    摘要翻译： 提供了一种用于在无线通信系统中进行信令和检测的系统和方法。 一种用于处理信息的方法包括在第一阶段中操作，在第二阶段中操作，以及处理检测到的信息。 第一阶段包括对接收到的信号迭代地反转第一滤波操作，并且第二阶段包括对考虑到第一用户的符号的第一估计误差和接收到的符号的第二估计误差的接收信号的第二滤波操作迭代地反相 第二个用户。

    System and method for signaling and detecting in wireless communications systems
    2.
    发明授权
    System and method for signaling and detecting in wireless communications systems 有权
    用于无线通信系统中的信令和检测的系统和方法

    公开(公告)号：US08724746B2

    公开(公告)日：2014-05-13

    申请号：US13050437

    申请日：2011-03-17

    申请人： Christian Schlegel ,  Carmela Cozzo

    发明人： Christian Schlegel ,  Carmela Cozzo

    IPC分类号： H04L27/06

    CPC分类号： H04L25/03305

    摘要： A system and method for signaling and detecting in wireless communications systems are provided. A method for processing information includes operating in a first phase, operating in a second phase, and processing the detected information. The first phase includes iteratively inverting a first filtering operation on received signals, and the second phase includes iteratively inverting a second filtering operation on received signals with consideration given to a first estimation error of symbols of the first user and a second estimation error of symbols of the second user.

    摘要翻译： 提供了一种用于在无线通信系统中进行信令和检测的系统和方法。 一种用于处理信息的方法包括在第一阶段中操作，在第二阶段中操作，以及处理检测到的信息。 第一阶段包括对接收到的信号迭代地反转第一滤波操作，并且第二阶段包括对考虑到第一用户的符号的第一估计误差和接收到的符号的第二估计误差的接收信号的第二滤波操作迭代地反相 第二个用户。

    Low-voltage CMOS circuits for analog decoders
    3.
    发明申请
    Low-voltage CMOS circuits for analog decoders 失效
    用于模拟解码器的低压CMOS电路

    公开(公告)号：US20070276895A9

    公开(公告)日：2007-11-29

    申请号：US11056063

    申请日：2005-02-10

    申请人： Chris Winstead ,  Christian Schlegel

    发明人： Chris Winstead ,  Christian Schlegel

    IPC分类号： G06F7/38

    CPC分类号： H03M13/3905 ,  H03M13/1102 ,  H03M13/1134 ,  H03M13/2957 ,  H03M13/6561 ,  H03M13/6597

    摘要： Low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits, suitable for analog decoders, for example, are provided. The circuits include multiplier modules that receive first input signals and respective ones of a plurality of second input signals. Each multiplier module generates as output signals products of the first input signals and its respective second input signals. Dummy multiplier modules that respectively correspond to the multiplier modules receive the second input signals, and each dummy multiplier module forms products of the second input signal of its corresponding multiplier module and the other second input signals. The dummy multiplier modules reduce the overall voltage requirements of the circuit, thereby providing for low-voltage operation. In some embodiments, a connectivity module receives output signals from the multiplier modules and generates as output signals sums of predetermined ones of the output signals, and a renormalization module receives and normalizes the output signals from the connectivity module to generate output signals that sum to a predetermined unit value.

    摘要翻译： 提供了适用于模拟解码器的低电压CMOS（互补金属氧化物半导体）电路。 电路包括接收第一输入信号和多个第二输入信号中相应的乘法器模块。 每个乘法器模块产生第一输入信号及其相应的第二输入信号的输出信号的产物。 分别对应于乘法器模块的虚拟乘法器模块接收第二输入信号，并且每个虚拟乘法器模块形成其对应的乘法器模块的第二输入信号和其它第二输入信号的乘积。 虚拟乘法器模块降低了电路的总体电压要求，从而提供低电压操作。 在一些实施例中，连接模块接收来自乘法器模块的输出信号，并且产生作为输出信号的预定输出信号的和的重新归一化模块接收和归一化来自连接模块的输出信号，以产生与 预定单位价值。

    LOW V2O5 - CONTENT AND V2O5 - FREE PORCELAIN ENAMELS
    6.
    发明申请
    LOW V2O5 - CONTENT AND V2O5 - FREE PORCELAIN ENAMELS 有权
    低V2O5 - 含量和V2O5 - 免费PORCELAIN ENAMELS

    公开(公告)号：US20110129679A1

    公开(公告)日：2011-06-02

    申请号：US12993113

    申请日：2009-08-12

    申请人： Efimenko Svetlana ,  Nancy Crevits ,  Christian Schlegel

    发明人： Efimenko Svetlana ,  Nancy Crevits ,  Christian Schlegel

    IPC分类号： C03C8/08 ,  C03C8/14 ,  B32B15/04

    CPC分类号： C03C8/12 ,  C03C3/064 ,  C03C8/14 ,  C03C2207/04 ,  C03C2207/08 ,  C03C2207/10 ,  C23D5/02

    摘要： The present invention relates to a low-V2O5-content and even V2O5-free porcelain enamel with improved dish-washer resistance, very good acid resistance and good adherence on various substrates. The invention moreover relates to a transparent low-V2O5-content and even V2O5-free porcelain enamel frit for application of enamel coatings with infinite colour range on a substrate made of aluminium, cast aluminium, aluminium alloy, aluminium-magnesium alloy, cast aluminium alloy, copper, austenitic stainless steel and mild steel, presenting improved dish-washer resistance, good acid resistance and good adherence on the substrate.The composition of the porcelain enamel in question comprises about 30 wt-% to about 50 wt-% SiO2, about 30 wt-% to about 40 wt-% R2O, about 15 wt-% to about 25 wt-% TiO2, about 0 wt-% to about 5 wt-% RO, about 0 wt-% to about 4 wt-% V2O5, about 0.3 wt-% to about 7 wt-% Fe2O3, about 0 wt-% to about 3 wt-% Sb2O3, about 0 wt-% to about 3 wt-% SnO2, about 0 wt-% to about 2 wt-% B2O3, about 0 wt-% to about 3 wt-% Al2O3, about 0 wt-% to about 4 wt-% P2O5, about 0 wt-% to about 1 wt-% MoO3, about 0 wt-% to about 2 wt-% F2, about 0 wt-% to about 4 wt-% ZrO2, about 0 wt-% to about 4 wt-% ZnO, about 0 wt-% to about 6 wt-% NOx, R2O is a combination of alkaline oxides selected from the group of: Na2O 10-23 mol %, K2O 7-20 mol % and Li2O 1-6.5 mol %, wherein RO represent at least one earth alkali oxide and wherein the molar ratio of (Li2O+B2O3) to TiO2 amounts to 0.2 to 0.6.

    摘要翻译： 本发明涉及一种低V2O5含量甚至无V2O5的瓷搪瓷，具有改善的洗碗机阻力，非常好的耐酸性和在各种基材上的良好粘附性。 此外，本发明还涉及一种透明的低V2O5含量甚至V2O5的瓷釉料，用于在由铝，铸铝，铝合金，铝镁合金，铸铝合金制成的基材上应用具有无限色彩范围的搪瓷涂层 ，铜，奥氏体不锈钢和低碳钢，具有改善的洗衣机阻力，良好的耐酸性和对基材的良好粘附性。 所述瓷釉的组成包含约30重量％至约50重量％的SiO 2，约30重量％至约40重量％的R 2 O，约15重量％至约25重量％的TiO 2，约0 重量％至约5重量％的RO，约0重量％至约4重量％的V 2 O 5，约0.3重量％至约7重量％的Fe 2 O 3，约0重量％至约3重量％的Sb 2 O 3， 约0重量％至约3重量％的SnO 2，约0重量％至约2重量％的B 2 O 3，约0重量％至约3重量％的Al 2 O 3，约0重量％至约4重量％ 约0重量％至约1重量％的MoO 3，约0重量％至约2重量％的F2，约0重量％至约4重量％的ZrO 2，约0重量％至约4重量％ - ％ZnO，约0重量％至约6重量％的NOx，R2O是选自以下的碱性氧化物的组合：Na 2 O 10-23摩尔％，K 2 O 7-20摩尔％和Li 2 O 1-6.5摩尔％ 其中RO代表至少一种碱土金属氧化物，其中（Li 2 O + B 2 O 3）与TiO 2的摩尔比为0.2-0.6。

    SIGNAL FILTERING AND FILTER DESIGN TECHNIQUES
    7.
    发明申请
    SIGNAL FILTERING AND FILTER DESIGN TECHNIQUES 审中-公开
    信号滤波和滤波器设计技术

    公开(公告)号：US20110113082A1

    公开(公告)日：2011-05-12

    申请号：US12449432

    申请日：2008-02-07

    申请人： Amirhossein Alimohammad ,  Saeed Fouladi Fard ,  Bruce Fordyce Cockburn ,  Christian Schlegel

    发明人： Amirhossein Alimohammad ,  Saeed Fouladi Fard ,  Bruce Fordyce Cockburn ,  Christian Schlegel

    IPC分类号： G06F17/10

    CPC分类号： H03H17/0292 ,  H03H17/04 ,  H03H17/0621 ,  H03H2218/12

    摘要： Signal filtering and filter design techniques are disclosed. An interconnection circuit switchably couples an input and an output of an element that is operable to perform a signal filtering operation on a signal received at the input so as to provide a filtered signal at the output. This enables the element to be used to implement a series of cascaded signal filtering operations. An iterative filter design method and a data structure that enables control of the element and/or the interconnection circuit are also disclosed. According to another aspect of the invention, an element is operable to perform any of multiple signal filtering operations on a received input signal. Controlled selection of respective sets of filter parameters associated with the multiple signal filtering operations enables the element to be used to implement the signal filtering operations in parallel filtering paths.

    摘要翻译： 公开了信号滤波和滤波器设计技术。 互连电路可切换地耦合可操作以对在输入端接收到的信号执行信号滤波操作的元件的输入和输出，以在输出端提供滤波信号。 这使得该元件可用于实现一系列级联信号滤波操作。 还公开了能够控制元件和/或互连电路的迭代滤波器设计方法和数据结构。 根据本发明的另一方面，元件可操作以对接收到的输入信号执行多个信号滤波操作中的任何一个。 与多个信号滤波操作相关联的各组滤波器参数的受控选择使得能够使用该元件来实现并行滤波路径中的信号滤波操作。

    Low-voltage CMOS circuits for analog decoders
    8.
    发明授权
    Low-voltage CMOS circuits for analog decoders 失效
    用于模拟解码器的低压CMOS电路

    公开(公告)号：US07418468B2

    公开(公告)日：2008-08-26

    申请号：US11056063

    申请日：2005-02-10

    申请人： Chris J. Winstead ,  Christian Schlegel

    发明人： Chris J. Winstead ,  Christian Schlegel

    IPC分类号： G06F7/52 ,  G06G7/16 ,  H03M13/00

    CPC分类号： H03M13/3905 ,  H03M13/1102 ,  H03M13/1134 ,  H03M13/2957 ,  H03M13/6561 ,  H03M13/6597

    摘要： Low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits, suitable for analog decoders, for example, are provided. The circuits include multiplier modules that receive first input signals and respective ones of a plurality of second input signals. Each multiplier module generates as output signals products of the first input signals and its respective second input signals. Dummy multiplier modules that respectively correspond to the multiplier modules receive the second input signals, and each dummy multiplier module forms products of the second input signal of its corresponding multiplier module and the other second input signals. The dummy multiplier modules reduce the overall voltage requirements of the circuit, thereby providing for low-voltage operation. In some embodiments, a connectivity module receives output signals from the multiplier modules and generates as output signals sums of predetermined ones of the output signals, and a renormalization module receives and normalizes the output signals from the connectivity module to generate output signals that sum to a predetermined unit value.

    摘要翻译： 提供了适用于模拟解码器的低电压CMOS（互补金属氧化物半导体）电路。 电路包括接收第一输入信号和多个第二输入信号中相应的乘法器模块。 每个乘法器模块产生第一输入信号及其相应的第二输入信号的输出信号的产物。 分别对应于乘法器模块的虚拟乘法器模块接收第二输入信号，并且每个虚拟乘法器模块形成其对应的乘法器模块的第二输入信号和其它第二输入信号的乘积。 虚拟乘法器模块降低了电路的总体电压要求，从而提供低电压操作。 在一些实施例中，连接模块接收来自乘法器模块的输出信号，并且产生作为输出信号的预定输出信号的和的重新归一化模块接收和归一化来自连接模块的输出信号，以产生与 预定单位价值。

    Lead-, cadmium- and barium-free frits for ceramic glazes
    9.
    发明授权
    Lead-, cadmium- and barium-free frits for ceramic glazes 失效
    陶瓷釉料的铅，镉和无钡玻璃料

    公开(公告)号：US5264398A

    公开(公告)日：1993-11-23

    申请号：US923568

    申请日：1992-08-03

    申请人： Peter Thometzek ,  Christian Schlegel

    发明人： Peter Thometzek ,  Christian Schlegel

    IPC分类号： C03C8/04

    CPC分类号： C03C8/04

    摘要： A frit composition for ceramic glazes is disclosed which is free of lead, cadmium and also barium. The composition contains SiO.sub.2, B.sub.2 O.sub.3, Al.sub.2 O.sub.3, alkali metal oxide, CaO, ZnO, and optionally MgO, SrO, TiO.sub.2, Bi.sub.2 O.sub.3, P.sub.2 O.sub.5 or ZrO.sub.2.

    摘要翻译： 公开了一种不含铅，镉和钡的陶瓷釉料玻璃料组合物。 该组合物含有SiO 2，B 2 O 3，Al 2 O 3，碱金属氧化物，CaO，ZnO，以及任选的MgO，SrO，TiO 2，Bi 2 O 3，P 2 O 5或ZrO 2。