-
公开(公告)号：US08862086B2
公开(公告)日：2014-10-14
申请号：US13453162
申请日：2012-04-23
CPC分类号： H03D7/1433 , H03D7/125 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/006 , H03D2200/0068
摘要： A mixer is configured to sample a received input signal at a predefined oscillator frequency to generate a sampled input signal, and to switch a polarity of the sampled input signal at a predefined polarity switching frequency to generate a polarity switched sampled input signal.
摘要翻译： 混频器被配置为以预定的振荡器频率对接收到的输入信号进行采样以产生采样的输入信号，并且以预定的极性切换频率切换采样的输入信号的极性，以产生极性切换采样的输入信号。
-
公开(公告)号：US20120270518A1
公开(公告)日：2012-10-25
申请号：US13453162
申请日：2012-04-23
IPC分类号： H04B1/16
CPC分类号： H03D7/1433 , H03D7/125 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/006 , H03D2200/0068
摘要： A mixer is configured to sample a received input signal at a predefined oscillator frequency to generate a sampled input signal, and to switch a polarity of the sampled input signal at a predefined polarity switching frequency to generate a polarity switched sampled input signal.
摘要翻译： 混频器被配置为以预定的振荡器频率对接收到的输入信号进行采样以产生采样的输入信号，并且以预定的极性切换频率切换采样的输入信号的极性，以产生极性切换采样的输入信号。
-
公开(公告)号：US08848847B2
公开(公告)日：2014-09-30
申请号：US13443394
申请日：2012-04-10
IPC分类号： H04B1/10
CPC分类号： H03D7/125 , H03D2200/0062 , H03H17/0227 , H03H17/06 , H03H2015/007 , H03H2017/0692
摘要： One embodiment of the present invention relates to a combined mixer filter circuit. The circuit includes a sampler, a plurality of filter branches, and a coefficient generator. The sampler is configured to provide a sampled signal by sampling a received signal at a specified rate. The plurality of filter branches has selectable filter coefficients. The plurality of filter branches are configured to receive the sampled signal and generate a mixed and filtered output signal without a separate mixer component. The coefficient generator is coupled to the plurality of filter branches. The coefficient generator is configured to assign filter coefficient values to the selectable filter coefficients to yield a selected mixing function for the mixed filtered output signal.
摘要翻译： 本发明的一个实施例涉及组合式混合器滤波器电路。 电路包括采样器，多个滤波器分支和系数发生器。 采样器被配置为通过以指定的速率对接收到的信号进行采样来提供采样信号。 多个滤波器分支具有可选择的滤波器系数。 多个滤波器分支被配置为接收采样信号，并产生混合和滤波的输出信号而没有单独的混频器部件。 系数发生器耦合到多个滤波器分支。 系数发生器被配置为将滤波器系数值分配给可选择的滤波器系数，以产生用于混合滤波输出信号的选择的混频功能。
-
公开(公告)号：US20130266101A1
公开(公告)日：2013-10-10
申请号：US13443394
申请日：2012-04-10
IPC分类号： H04B1/10
CPC分类号： H03D7/125 , H03D2200/0062 , H03H17/0227 , H03H17/06 , H03H2015/007 , H03H2017/0692
摘要： One embodiment of the present invention relates to a combined mixer filter circuit. The circuit includes a sampler, a plurality of filter branches, and a coefficient generator. The sampler is configured to provide a sampled signal by sampling a received signal at a specified rate. The plurality of filter branches has selectable filter coefficients. The plurality of filter branches are configured to receive the sampled signal and generate a mixed and filtered output signal without a separate mixer component. The coefficient generator is coupled to the plurality of filter branches. The coefficient generator is configured to assign filter coefficient values to the selectable filter coefficients to yield a selected mixing function for the mixed filtered output signal.
摘要翻译： 本发明的一个实施例涉及组合式混合器滤波器电路。 电路包括采样器，多个滤波器分支和系数发生器。 采样器被配置为通过以指定的速率对接收到的信号进行采样来提供采样信号。 多个滤波器分支具有可选择的滤波器系数。 多个滤波器分支被配置为接收采样信号，并产生混合和滤波的输出信号而没有单独的混频器部件。 系数发生器耦合到多个滤波器分支。 系数发生器被配置为将滤波器系数值分配给可选择的滤波器系数，以产生用于混合滤波输出信号的选择的混频功能。
-
公开(公告)号：US20100177811A1
公开(公告)日：2010-07-15
申请号：US12352773
申请日：2009-01-13
CPC分类号： H04B1/40
摘要： This disclosure relates to radio frequency (RF) functional testing of transceivers of wireless devices.
摘要翻译： 本公开涉及无线设备的收发器的射频（RF）功能测试。
-
6.发明授权Compensation of phase lock loop (PLL) phase distribution caused by power amplifier ramping 有权由功率放大器斜坡引起的锁相环（PLL）相位分布补偿公开(公告)号：US08058917B2
公开(公告)日：2011-11-15
申请号：US12483708
申请日：2009-06-12
申请人： Thomas Mayer , Rainer Kreienkamp , Jens Kissing
发明人： Thomas Mayer , Rainer Kreienkamp , Jens Kissing
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03L7/099 , H03L7/1976 , H03L2207/06 , H03L2207/50
摘要： Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.
摘要翻译： 这里公开了与功率放大器的功率斜坡上升或下降期间相位锁定相位补偿相关的技术，系统和方法。 更具体地说，描述了能够根据功率放大器的功率状态在I型和II型PLL模式之间切换而不引入附加干扰的锁相环。
-
7.发明申请COMPENSATION OF PHASE LOCK LOOP (PLL) PHASE DISTRIBUTION CAUSED BY POWER AMPLIFIER RAMPING 审中-公开功率放大器放大引起的相位锁相环（PLL）相位分配补偿公开(公告)号：US20120092048A1
公开(公告)日：2012-04-19
申请号：US13280610
申请日：2011-10-25
申请人： Thomas MAYER , Rainer Kreienkamp , Jens Kissing
发明人： Thomas MAYER , Rainer Kreienkamp , Jens Kissing
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03L7/099 , H03L7/1976 , H03L2207/06 , H03L2207/50
摘要： Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.
摘要翻译： 这里公开了与功率放大器的功率斜坡上升或下降期间相位锁定相位补偿相关的技术，系统和方法。 更具体地说，描述了能够根据功率放大器的功率状态在I型和II型PLL模式之间切换而不引入附加干扰的锁相环。
-
公开(公告)号：US08780959B2
公开(公告)日：2014-07-15
申请号：US12352773
申请日：2009-01-13
CPC分类号： H04B1/40
摘要： This disclosure relates to radio frequency (RF) functional testing of transceivers of wireless devices.
摘要翻译： 本公开涉及无线设备的收发器的射频（RF）功能测试。
-
9.发明申请Compensation Of Phase Lock Loop (PLL) Phase Distribution Caused By Power Amplifier Ramping 有权由功率放大器斜坡引起的锁相环（PLL）相位分布补偿公开(公告)号：US20100315140A1
公开(公告)日：2010-12-16
申请号：US12483708
申请日：2009-06-12
申请人： Thomas Mayer , Rainer Kreienkamp , Jens Kissing
发明人： Thomas Mayer , Rainer Kreienkamp , Jens Kissing
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03L7/099 , H03L7/1976 , H03L2207/06 , H03L2207/50
摘要： Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.
摘要翻译： 这里公开了与功率放大器的功率斜坡上升或下降期间相位锁定相位补偿相关的技术，系统和方法。 更具体地说，描述了能够根据功率放大器的功率状态在I型和II型PLL模式之间切换而不引入附加干扰的锁相环。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.018 秒)
