Reduction of data skew in parallel processing circuits
    2.
    发明授权
    Reduction of data skew in parallel processing circuits 有权
    减少并行处理电路中的数据偏移

    公开(公告)号:US07496780B2

    公开(公告)日:2009-02-24

    申请号:US10364763

    申请日:2003-02-11

    IPC分类号: G06F1/12

    CPC分类号: H04J3/04 H04J3/0685 H04L25/14

    摘要: Signal processing circuitry having parallel processing channels has clock-generation circuitry that generates (i) high-speed clock signals used to drive the channels and (ii) synchronization signals used to reset the processing of the channels. In one embodiment, the signal processing circuitry has multiple multiplexing channels arranged in one or more macrocells, each macrocell having one or more channels and a phase-locked loop (PLL) that generates a high-speed PLL clock signal and a synchronization signal for the macrocell's channels. Each channel has a counter that implements a state machine used to drive the multiplexing processing, where the state machine is reset to a specified state upon receipt of each synchronization pulse in the synchronization signal.

    摘要翻译: 具有并行处理通道的信号处理电路具有产生(i)用于驱动信道的高速时钟信号和(ii)用于复位通道处理的同步信号的时钟生成电路。 在一个实施例中,信号处理电路具有布置在一个或多个宏小区中的多个复用信道,每个宏小区具有一个或多个信道,以及产生高速PLL时钟信号和同步信号的锁相环(PLL) 宏单元的渠道。 每个通道具有实现用于驱动多路复用处理的状态机的计数器,其中在接收到同步信号中的每个同步脉冲时状态机被复位到指定状态。

    Method and apparatus for sigma-delta delay control in a delay-locked-loop
    3.
    发明授权
    Method and apparatus for sigma-delta delay control in a delay-locked-loop 失效
    延迟锁定环路中Σ-Δ延迟控制的方法和装置

    公开(公告)号:US07330060B2

    公开(公告)日:2008-02-12

    申请号:US11221387

    申请日:2005-09-07

    IPC分类号: H03L7/06

    摘要: Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is generated if a clock signal has a time lag relative to a reference signal. The first and second values are accumulated to generate an N bit digital word; and the N bit digital word is reduced to an M bit digital word, where M is less than N. Thereafter, the M bit digital word can be converted to an analog bias signal. The reducing step can be performed, for example, by a sigma-delta modulator. The high frequency quantization noise generated by the sigma-delta modulator can be filtered using a low pass filter. The converting step can be performed by a digital-to-analog converter, such as a master/slave digital-to-analog converter.

    摘要翻译: 提供了延迟锁定环中的Σ-Δ延迟控制的方法和装置,其采用延迟线来基于参考信号产生时钟信号。 如果时钟信号相对于参考信号具有时间导通,则产生第一值; 并且如果时钟信号相对于参考信号具有时滞,则产生第二值。 累积第一和第二值以产生N位数字字; 并将N位数字字减少为M位数字字,其中M小于N.此后,M位数字字可以转换为模拟偏置信号。 还原步骤可以由例如Σ-Δ调制器进行。 可以使用低通滤波器对由Σ-Δ调制器产生的高频量化噪声进行滤波。 转换步骤可以由诸如主/从数字模拟转换器之类的数 - 模转换器执行。

    Phase interpolator with output amplitude correction
    5.
    发明授权
    Phase interpolator with output amplitude correction 有权
    具有输出幅度校正的相位内插器

    公开(公告)号:US07425856B2

    公开(公告)日:2008-09-16

    申请号:US11479749

    申请日:2006-06-30

    IPC分类号: H03H11/16

    摘要: A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.

    摘要翻译: 相位插值器从两个相位偏移输入时钟信号A和B产生相位插值输出时钟信号Z,其中输出时钟的插值角基于权重值W.相位内插器具有A侧和B- 每个电路具有(1)并联电流镜阵列,(2)一组并联开关,其中每个开关与相应的电流镜串联连接,以及(3)编码器,其基于 重量值W.通过相位内插器的总电流随内插角度变化,使得例如,具有内插角度的输出幅度的变化减小。 通常,重量值W中的各个位值不用于控制各个开关的所有插补角度。

    Methods and apparatus for serializer/deserializer transmitter synchronization
    6.
    发明授权
    Methods and apparatus for serializer/deserializer transmitter synchronization 有权
    串行器/解串器发射机同步的方法和装置

    公开(公告)号:US08165253B2

    公开(公告)日:2012-04-24

    申请号:US12200106

    申请日:2008-08-28

    IPC分类号: H04L7/00

    CPC分类号: H04J3/0685

    摘要: Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.

    摘要翻译: 提供串行器/解串器发射机同步的方法和装置。 通过在一个或多个信道中产生同步请求,在一个或多个串行器/解串器设备中同步多个信道; 响应于所述同步请求产生使能信号; 以及响应于使能信号,仅产生一个同步信号的一个或多个周期的门控同步信号。 门控同步信号可以可选地在同步信号的一个或多个周期之后被断言。

    METHODS AND APPARATUS FOR SERIALIZER/DESERIALIZER TRANSMITTER SYNCHRONIZATION
    7.
    发明申请
    METHODS AND APPARATUS FOR SERIALIZER/DESERIALIZER TRANSMITTER SYNCHRONIZATION 有权
    串行/解复用器发射机同步的方法和装置

    公开(公告)号:US20100054386A1

    公开(公告)日:2010-03-04

    申请号:US12200106

    申请日:2008-08-28

    IPC分类号: H04L7/00

    CPC分类号: H04J3/0685

    摘要: Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.

    摘要翻译: 提供串行器/解串器发射机同步的方法和装置。 通过在一个或多个信道中产生同步请求,在一个或多个串行器/解串器设备中同步多个信道; 响应于所述同步请求产生使能信号; 以及响应于使能信号,仅产生一个同步信号的一个或多个周期的门控同步信号。 门控同步信号可以可选地在同步信号的一个或多个周期之后被断言。

    Alternating clock signal generation for delay loops
    8.
    发明授权
    Alternating clock signal generation for delay loops 失效
    用于延迟环的交替时钟信号生成

    公开(公告)号:US07236037B2

    公开(公告)日:2007-06-26

    申请号:US11138777

    申请日:2005-05-26

    IPC分类号: H03K3/00

    摘要: A delay loop (e.g., a voltage-controlled delay loop) has (at least) two devices (e.g., interpolators) for generating clock signals for injection into the delay elements of the delay loop in a leap-frog manner, in which, while one interpolator is generating the clock signal currently selected for injection, the other interpolator can be controlled to generate the next clock signal to be selected for injection. This leap-frog technique can provide more settling time for generating injected clock signals than implementations that rely on a single interpolator.

    摘要翻译: 延迟环路(例如,电压控制延迟环路)具有(至少)两个用于产生用于以跳跃方式注入到延迟环路的延迟元件中的时钟信号的器件(例如,内插器),其中, 一个内插器正在产生当前被选择用于注入的时钟信号,另一个内插器可被控制以产生要被选择用于注入的下一个时钟信号。 这种跳跃式技术可以提供更多的建立时间来产生注入的时钟信号,而不是依赖于单个内插器的实现。

    Method and apparatus for determining one or more channel compensation parameters based on data eye monitoring
    9.
    发明授权
    Method and apparatus for determining one or more channel compensation parameters based on data eye monitoring 有权
    用于基于数据眼睛监测来确定一个或多个信道补偿参数的方法和装置

    公开(公告)号:US08861580B2

    公开(公告)日:2014-10-14

    申请号:US11434687

    申请日:2006-05-16

    IPC分类号: H03H7/30 H04L25/03 H04L1/20

    摘要: Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for evaluating the quality of a data eye associated with a signal. The received signal is sampled for a plurality of different phases, for example, using at least two latches, and the samples are evaluated to identify when the signal crosses a predefined amplitude value, such as a zero crossing. It is determined whether the points of predefined amplitude crossing satisfy one or more predefined criteria. One or more parameters of one or more channel compensation techniques can optionally be adjusted based on a result of the determining step. One or more parameters of an adjacent transmitter can also be adjusted to reduce near end cross talk based on a result of the determining step.

    摘要翻译: 提供了用于基于数据眼睛监测来确定一个或多个信道补偿参数的方法和装置。 根据本发明的一个方面,提供了一种用于评估与信号相关联的数据眼的质量的方法。 对于多个不同的相位,例如使用至少两个锁存器对接收到的信号进行采样,并且评估采样以识别信号何时跨越预定义的幅度值,例如零交叉。 确定预定义的幅度交叉点是否满足一个或多个预定标准。 一个或多个信道补偿技术的一个或多个参数可以根据确定步骤的结果来任意地进行调整。 也可以根据确定步骤的结果,调整相邻发射机的一个或多个参数以减少近端串扰。

    Methods and apparatus for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns
    10.
    发明授权
    Methods and apparatus for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns 失效
    具有可编程自适应模式的连续时间决策反馈均衡器的适应方法和装置

    公开(公告)号:US08483266B2

    公开(公告)日:2013-07-09

    申请号:US12847700

    申请日:2010-07-30

    IPC分类号: H03K5/159

    摘要: Methods and apparatus are provided for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns. A continuous time-decision feedback equalizer is adapted by obtaining at least one programmable signature pattern that triggers adaptation of one or more of a pole and a gain of the continuous time-decision feedback equalizer; detecting the at least one programmable signature pattern in an incoming signal; and adapting one or more of the pole and the gain of the continuous time-decision feedback equalizer when the at least one programmable signature pattern is detected in the incoming signal. The programmable signature pattern can be selected to ensure an unambiguous direction of change in an error sample when a corresponding one of the pole and the gain are modified.

    摘要翻译: 提供方法和装置用于适应具有可编程自适应模式的连续时间 - 决策反馈均衡器。 通过获得触发连续时间判定反馈均衡器的极点和增益中的一个或多个的自适应的至少一个可编程签名模式来适配连续时间判定反馈均衡器; 检测输入信号中的至少一个可编程签名模式; 以及当在所述输入信号中检测到所述至少一个可编程签名模式时,使所述连续时间判定反馈均衡器的极点和增益中的一个或多个被适配。 可以选择可编程签名模式,以确保当修正了极点和增益中的相应一个时,错误样本中的明确的变化方向。