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公开(公告)号：US07739538B2
公开(公告)日：2010-06-15
申请号：US11426651
申请日：2006-06-27
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译： 一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。 每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。 首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。 数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。 在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。 这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。
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公开(公告)号：US20070300095A1
公开(公告)日：2007-12-27
申请号：US11426651
申请日：2006-06-27
IPC分类号： G06F1/12
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译： 一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。 每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。 首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。 数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。 在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。 这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。
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公开(公告)号：US07882322B2
公开(公告)日：2011-02-01
申请号：US11426675
申请日：2006-06-27
CPC分类号： G06F13/4059 , G06F12/0855 , G06F12/0864
摘要： A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.
摘要翻译： 一种用于组织和使用通过双数据速率接口发送的数据的系统和方法，使得系统操作不会经历时间惩罚。 数据的第一个循环独立于第二个周期使用，以便等待时间不会受到损害。 有很多应用程序。 在L2高速缓存的优选实施例中，系统在前半部分发送同余类数据，并且可以开始以一致类数据访问L2高速缓存目录。
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公开(公告)号：US07752475B2
公开(公告)日：2010-07-06
申请号：US11426671
申请日：2006-06-27
CPC分类号： G06F13/4059
摘要： A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.
摘要翻译： 双数据速率接口，其中针对数据相对于另一数据路径延迟数据路径的设置间隔进行扩展。 数据被锁存到由中间循环型锁存器组成的寄存器中，例如L2 *锁存器。 例如，如果延迟的一半数据在双倍数据速率周期的下半部分之前不可用，则数据的后半部分被允许具有围绕中间周期点的建立间隔，同时片内定时 在建立之后，逻辑在时钟沿启动最少延迟的一半数据，而不用等待延迟数据的设置间隔的到期。
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公开(公告)号：US20070300096A1
公开(公告)日：2007-12-27
申请号：US11426671
申请日：2006-06-27
IPC分类号： G06F1/12
CPC分类号： G06F13/4059
摘要： A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.
摘要翻译： 双数据速率接口，其中针对数据相对于另一数据路径延迟数据路径的设置间隔进行扩展。 数据被锁存到由中间循环型锁存器组成的寄存器中，例如L2 *锁存器。 例如，如果延迟的一半数据在双倍数据速率周期的下半部分之前不可用，则数据的后半部分被允许具有围绕中间周期点的建立间隔，同时片内定时 在建立之后，逻辑在时钟沿启动最少延迟的一半数据，而不用等待延迟数据的设置间隔的到期。
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公开(公告)号：US20070300032A1
公开(公告)日：2007-12-27
申请号：US11426675
申请日：2006-06-27
IPC分类号： G06F13/00
CPC分类号： G06F13/4059 , G06F12/0855 , G06F12/0864
摘要： A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.
摘要翻译： 一种用于组织和使用通过双数据速率接口发送的数据的系统和方法，使得系统操作不会经历时间惩罚。 数据的第一个循环独立于第二个周期使用，以便等待时间不会受到损害。 有很多应用程序。 在L2高速缓存的优选实施例中，系统在前半部分发送同余类数据，并且可以开始以一致类数据访问L2高速缓存目录。
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公开(公告)号：US07269806B2
公开(公告)日：2007-09-11
申请号：US11408228
申请日：2006-04-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译： 用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。 该方法采用以下技术; a）通过层级降级并将设计划分为可变尺寸网格的方法; b）确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容器的算法; c）确定哪些网格位置受到有害的相邻影响的算法; 以及d）以图形方式显示计算结果的方法，以便容易地识别问题区域。
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公开(公告)号：US07086026B2
公开(公告)日：2006-08-01
申请号：US10436393
申请日：2003-05-12
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques: 1. A method for descending through hierarchy and dividing the design into a variable sized grid. 2. An algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location. 3. An algorithm to determine which grid locations are subject to harmful neighboring effects. 4. A method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译： 用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。 该方法采用以下技术：1.一种通过层级降级并将设计划分为可变尺寸网格的方法。 2.一种用于确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容的算法。 3.确定哪些网格位置受到有害的相邻影响的算法。 4.以图形方式显示计算结果的方法，以便轻松识别问题区域。
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公开(公告)号：US07346877B2
公开(公告)日：2008-03-18
申请号：US11408217
申请日：2006-04-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： This method for decoupling capacitance analysis improves upon existing techniques to attempt to give a more accurate representation of the power supply fluctuations on a chip while keeping runtime comparable. This method employs the following techniques; a) a method for descending through hierarchy and dividing the design into a variable sized grid; b) an algorithm to determine which grid locations of a design don't have enough decoupling capacitors for all of the devices in that grid location; c) an algorithm to determine which grid locations are subject to harmful neighboring effects; and d) a method to display the results of the calculations in a graphical manor to allow easy identification of problem areas.
摘要翻译： 用于去耦电容分析的这种方法改进了现有技术，以试图给出对芯片上的电源波动的更准确的表示，同时保持运行时可比性。 该方法采用以下技术; a）通过层级降级并将设计划分为可变尺寸网格的方法; b）确定设计的哪些网格位置对于该网格位置中的所有设备没有足够的去耦电容器的算法; c）确定哪些网格位置受到有害的相邻影响的算法; 以及d）以图形方式显示计算结果的方法，以便容易地识别问题区域。
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公开(公告)号：US08299610B1
公开(公告)日：2012-10-30
申请号：US11971577
申请日：2008-01-09
IPC分类号： H01L23/12
CPC分类号： H01L23/552 , H01L23/13 , H01L23/29 , H01L23/3128 , H01L23/5389 , H01L24/48 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/81801 , H01L2224/83 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15159 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/3025 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface of the substrate. A conductive coating is applied to the mold compound and to at least one metal layer exposed on at least one side surface of the substrate.
摘要翻译： 半导体器件和制造方法具有具有多个金属层的衬底。 至少一个金属层暴露在半导体器件的至少一个侧表面上。 模具耦合到基板。 模具化合物封装模具和衬底的顶表面。 将导电涂层施加到模制化合物和暴露于基底的至少一个侧表面上的至少一个金属层。
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