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公开(公告)号：US6107852A
公开(公告)日：2000-08-22
申请号：US81001
申请日：1998-05-19
CPC分类号： H03K3/012 , H03K3/356156
摘要： A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.
摘要翻译： 公开了一种用于减少与用于在数据处理系统中实现集成电路的电路中插入锁存相关联的惩罚的方法和装置。 公开了一种半导体器件，其包括主锁存电路，反馈锁存电路和输出端子。 主锁存电路能够接收输入数据信号和输入时钟信号。 主锁存电路根据输入数据和时钟信号产生锁存输出信号。 反馈锁存电路能够接收来自主锁存电路的锁存输出信号并存储锁存器输出信号。 反馈锁存电路能够产生由主锁存电路接收的反馈锁存电路输出信号，以维持锁存输出信号。 设备的输出端耦合到反馈锁存电路，用于输出等于反馈锁存电路输出信号的器件输出信号。
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2.发明授权Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs 失效减少功率动态逻辑电路，抑制稳定输入的重新评估
公开(公告)号：US6037804A
公开(公告)日：2000-03-14
申请号：US049741
申请日：1998-03-27
申请人： Christopher McCall Durham , Visweswara Rao Kodali , Michael Ju Hyeok Lee , Douglas Ele Martin , Harsh Dev Sharma
发明人： Christopher McCall Durham , Visweswara Rao Kodali , Michael Ju Hyeok Lee , Douglas Ele Martin , Harsh Dev Sharma
IPC分类号： H03K19/00 , H03K19/096 , H03K19/094
CPC分类号： H03K19/096 , H03K19/0016
摘要： A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.
摘要翻译： 降低功率的集成电路包括电路数据输入，电路数据输出和至少一行动态逻辑。 动态逻辑行包括行时钟输入，行数据输入和耦合到电路数据输出的行数据输出，其中根据电路数据输入的值导出在行数据输入处接收的值。 集成电路还包括比较器，其比较电路数据输入端的当前值和先前值，以及开关，其选择性地将在行时钟输入处接收的行时钟信号设置为非活动状态，并将行时钟信号暂时保持在非活动状态 对比较器的响应检测到电路数据输入端的当前先前值是等效的。 因此，动态逻辑行（并不需要）重新评估电路数据输入值，并降低功耗。
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公开(公告)号：US06002271A
公开(公告)日：1999-12-14
申请号：US854368
申请日：1997-05-12
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： Circuitry for eliminating charge sharing noise in MOS dynamic logic circuits is described. Dynamic logic circuits having stacks of MOS devices controlling the state of a common node defining the output logic state of the circuit are susceptible to charge sharing noise. This noise ultimately arises from leakage and stray capacitances at the nodes between MOS devices in each stack which the common node must supply. The noise is eliminated by employing MOS devices associated with the MOS devices in the stacks to couple the nodes between stack MOS devices to a supply voltage until their associated stack device changes logic state. On the changing state of the associated stack device, the node charging MOS device turns off, allowing the nodes to assume states defined by the input signals to the dynamic logic circuit.
摘要翻译： 描述用于消除MOS动态逻辑电路中的电荷共享噪声的电路。 具有控制限定电路的输出逻辑状态的公共节点的状态的MOS器件堆叠的动态逻辑电路容易受到电荷共享噪声的影响。 这种噪声最终来自公共节点必须提供的每个堆叠中的MOS器件之间的节点处的泄漏和杂散电容。 通过使用与堆叠中的MOS器件相关联的MOS器件来消除噪声，以将堆叠MOS器件之间的节点耦合到电源电压，直到其相关联的堆栈器件改变逻辑状态。 在相关联的堆叠设备的变化状态下，节点充电MOS器件关闭，允许节点采取由输入信号定义到动态逻辑电路的状态。
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公开(公告)号：US6046606A
公开(公告)日：2000-04-04
申请号：US10200
申请日：1998-01-21
IPC分类号： H03K19/003 , G06F11/00 , H03K19/096 , H03K19/094 , H03K19/20
CPC分类号： G06F11/00 , G06F11/004
摘要： A method and apparatus is effective to preserve logic state potential levels in logic circuitry notwithstanding alpha particle collisions. Cross-coupled circuitry, including active devices, are implemented in a complementary logic circuit arrangement to hold current logic values in the event of a premature switching such as a switching that may be induced by alpha particle collision with the semiconductor logic circuit. Stabilizing transistor switching devices are arranged to sense an inappropriate or premature switching initiation and respond thereto by operating to maintain the appropriate logic levels within the logic circuitry. In one embodiment, the internal node of an upper circuit in a dual-rail logic circuit is connected to a gate terminal of a cross-coupled PFET device in the lower circuit. The cross-coupled PFET device is operable to sense an initiated untimely switching action in the upper circuit and effect a re-application of the holding PFET in the upper circuit to re-establish the appropriate logic potential levels in the upper circuit.
摘要翻译： 尽管存在α粒子碰撞，但是方法和装置有效地保持逻辑电路中的逻辑状态电位电平。 包括有源器件的交叉耦合电路在互补逻辑电路装置中实现，以在诸如可能由半导体逻辑电路的α粒子碰撞引起的切换的过早切换的情况下保持当前逻辑值。 稳定晶体管开关器件被布置为感测不适当或过早的开关启动，并通过操作来响应于其来维持逻辑电路内的适当的逻辑电平。 在一个实施例中，双轨逻辑电路中的上电路的内部节点连接到下电路中的交叉耦合PFET器件的栅极端子。 交叉耦合PFET器件可操作以感测上电路中引发的不合时宜的开关动作，并且实现上电路中保持PFET的重新施加，以重新建立上电路中适当的逻辑电位电平。
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公开(公告)号：US5852373A
公开(公告)日：1998-12-22
申请号：US723814
申请日：1996-09-30
IPC分类号： H03K19/0175 , H03K19/096 , H03K19/0948
CPC分类号： H03K19/0963
摘要： A dynamic logic circuit is capable of receiving both dynamic and static input signals during both the precharge and evaluate phases of the logic circuit, and the static input signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages and the logic circuit is still capable of correctly evaluating the implemented logical operation on the static and dynamic input signals. This is performed in CMOS by coupling a PFET between the internal precharge node and a voltage reference source where the gate electrode of the PFET device receives the static input signal.
摘要翻译： 动态逻辑电路能够在逻辑电路的预充电和评估阶段期间接收动态和静态输入信号，并且静态输入信号被允许从低电平切换到高电平和高电平 在这种阶段期间的低电平，并且逻辑电路仍然能够正确评估对静态和动态输入信号的实现的逻辑运算。 这通过在内部预充电节点和PFET器件的栅电极接收静态输入信号的电压参考源之间耦合PFET来实现。
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公开(公告)号：US07813189B2
公开(公告)日：2010-10-12
申请号：US12166421
申请日：2008-07-02
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22
摘要： A data input latch and clocking method and apparatus for high performance SRAM in which an L1 data input latch is controlled by a logical combination of the normal local clock buffer clock signal and the local array clock buffer clock signal. This logical combination of clock signals minimizes the hold time of the L1 latch provides a fast cycle time in which the SRAM macro can process successive write instructions while avoiding early mode issues.
摘要翻译： 一种用于高性能SRAM的数据输入锁存和时钟方法和装置，其中L1数据输入锁存器由正常本地时钟缓冲时钟信号和本地阵列时钟缓冲时钟信号的逻辑组合控制。 时钟信号的这种逻辑组合使得L1锁存器的保持时间最小化提供了快速周期时间，其中SRAM宏可以处理连续写指令，同时避免早期模式问题。
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7.发明授权Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation 失效动态静态逻辑控制元件，用于发出控制信号结束与逻辑评估之间的间隔公开(公告)号：US07015723B2
公开(公告)日：2006-03-21
申请号：US10922271
申请日：2004-08-19
IPC分类号： H03K19/00
CPC分类号： H03K19/0963
摘要： A dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation provides a compact circuit for blocking the indication of a non-evaluated state of a dynamic logic gate until a control signal has ended. The control signal is connected to a precharge input of the control element and a summing node is connected to one or more evaluation trees and to the control element output via an inverter. The inverter is connected to an override circuit that forces the output of the control element to a state opposite the precharge state until the control signal has ended. The output of the control element then assumes a state corresponding to the precharge state until an evaluation occurs. The control element output thus produces a window signal indicating the interval between the end of the control signal and the evaluation.
摘要翻译： 用于发信号通知控制信号的结束与逻辑评估之间的间隔的动态静态逻辑控制元件提供紧凑的电路，用于阻止动态逻辑门的未评估状态的指示，直到控制信号结束为止。 控制信号连接到控制元件的预充电输入，并且求和节点经由逆变器连接到一个或多个评估树和控制元件输出。 逆变器连接到超控电路，其将控制元件的输出强制到与预充电状态相反的状态，直到控制信号结束。 然后，控制元件的输出呈现与预充电状态相对应的状态，直到评估发生。 因此，控制元件输出产生指示控制信号的结束与评估之间的间隔的窗口信号。
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公开(公告)号：US07002860B2
公开(公告)日：2006-02-21
申请号：US10703017
申请日：2003-11-06
CPC分类号： G11C7/1012 , G11C7/1051 , G11C8/10
摘要： A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupled to respective output nodes. Each multiplexer has a logic gate with inputs coupled to respective multiplexer output nodes. A second decoder is coupled to an N+1th multiplexer having R output nodes and R pull-ups coupled thereto. The N+1th multiplexer also has N selectors, coupled to respective select lines of the second decoder and respective output logic gates of the N multiplexers. The N selectors are in R groups coupled to the R nodes. An output logic gate for N+1th multiplexer has R inputs coupled respectively to the R nodes. Each pull-up of the multiplexers drives its respective multiplexer output node responsive to an address-bit signal.
摘要翻译： 位读取装置包括第一解码器和N个多路复用器，每个具有与其耦合的Q个输出节点和Q个上拉电路。 各个复用器具有耦合到NxM个选择线和寄存器文件单元的M个选择器。 选择器处于耦合到相应输出节点的Q组中。 每个复用器具有逻辑门，其输入耦合到相应的多路复用器输出节点。 第二解码器耦合到具有耦合到其上的R个输出节点和R个上拉的第N + 1个多路复用器。 第N + 1个多路复用器还具有N个选择器，耦合到第二解码器的相应选择线和N个多路复用器的相应输出逻辑门。 N个选择器位于耦合到R个节点的R组中。 用于N + 1个多路复用器的输出逻辑门分别具有分别耦合到R个节点的R个输入。 多路复用器的每个上拉响应地址位信号驱动其相应的多路复用器输出节点。
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公开(公告)号：US07804728B2
公开(公告)日：2010-09-28
申请号：US12185234
申请日：2008-08-04
申请人： Michael Ju Hyeok Lee , Bao G Truong
发明人： Michael Ju Hyeok Lee , Bao G Truong
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C11/413
摘要： An information handling system (IHS) includes a processor with on-chip or off-chip SRAM array. After a read operation, a control circuit may instruct the SRAM array to conduct a precharge operation, or alternatively, instruct the SRAM array to conduct an equalize bitline voltage operation. A read operation may follow the precharge operation or the equalize bitline voltage operation. The control circuit may instruct the SRAM array to conduct an equalize bitline voltage operation if an equalized voltage of a bitline pair exhibits more that a predetermined amount of voltage. Otherwise, the control circuit instructs the SRAM array to conduct a precharge operation before the next read operation.
摘要翻译： 信息处理系统（IHS）包括具有片上或片外SRAM阵列的处理器。 在读取操作之后，控制电路可以指示SRAM阵列进行预充电操作，或者替代地指示SRAM阵列进行均衡的位线电压操作。 读取操作可以遵循预充电操作或均衡位线电压操作。 如果位线对的均衡电压显示出更多的预定量的电压，则控制电路可以指示SRAM阵列进行均衡的位线电压操作。 否则，控制电路指示SRAM阵列在下一次读取操作之前进行预充电操作。
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10.发明授权System and computer program for verifying performance of an array by simulating operation of edge cells in a full array model 有权系统和计算机程序，用于通过模拟完整阵列模型中边缘单元的操作来验证阵列的性能公开(公告)号：US07552413B2
公开(公告)日：2009-06-23
申请号：US12166811
申请日：2008-07-02
CPC分类号： G06F17/5022
摘要： A system and computer program for verifying performance of an array by simulating operation of edge cells in a full array model reduces the computation time required for complete design verification. The edge cells of the array (or each subarray if the array is partitioned) are subjected to a timing simulation while the center cells of the array are logically disabled, but remain in the circuit model, providing proper loading. Additional cells are specified for simulation if calculations indicate a worst-case condition due to a non-edge cell. Wordline arrivals are observed to determine worst-case rows for selection. For write operations, the difference between the wordline edges and the data edges is used to locate any non-edge “outlier” cells. For read operations, the wordline delays are summed with the bitline delays determined from edge column data to locate any outliers.
摘要翻译： 通过模拟全阵列模型中边缘单元的操作来验证阵列的性能的系统和计算机程序减少了完整设计验证所需的计算时间。 阵列的边缘单元（或阵列分割的每个子阵列）经受定时仿真，而阵列的中心单元在逻辑上被禁用，但保留在电路模型中，从而提供适当的加载。 如果计算指示由于非边缘单元造成的最坏情况，则指定额外的单元用于模拟。 观察到字线到达以确定最坏情况行进行选择。 对于写入操作，字边和数据边之间的差异用于定位任何非边缘“异常值”单元。 对于读取操作，字线延迟与从边沿列数据确定的位线延迟相加以定位任何异常值。
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