公开(公告)号：US6037804A

公开(公告)日：2000-03-14

申请号：US049741

申请日：1998-03-27

申请人： Christopher McCall Durham ,  Visweswara Rao Kodali ,  Michael Ju Hyeok Lee ,  Douglas Ele Martin ,  Harsh Dev Sharma

发明人： Christopher McCall Durham ,  Visweswara Rao Kodali ,  Michael Ju Hyeok Lee ,  Douglas Ele Martin ,  Harsh Dev Sharma

IPC分类号： H03K19/00 ,  H03K19/096 ,  H03K19/094

CPC分类号： H03K19/096 ,  H03K19/0016

摘要： A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.

摘要翻译： 降低功率的集成电路包括电路数据输入，电​​路数据输出和至少一行动态逻辑。 动态逻辑行包括行时钟输入，行数据输入和耦合到电路数据输出的行数据输出，其中根据电路数据输入的值导出在行数据输入处接收的值。 集成电路还包括比较器，其比较电路数据输入端的当前值和先前值，以及开关，其选择性地将在行时钟输入处接收的行时钟信号设置为非活动状态，并将行时钟信号暂时保持在非活动状态 对比较器的响应检测到电路数据输入端的当前先前值是等效的。 因此，动态逻辑行（并不需要）重新评估电路数据输入值，并降低功耗。

公开(公告)号：US06208907B1

公开(公告)日：2001-03-27

申请号：US09016653

申请日：1998-01-30

申请人： Christopher McCall Durham ,  Visweswara Rao Kodali ,  Douglas Ele Martin ,  Harsh Dev Sharma

发明人： Christopher McCall Durham ,  Visweswara Rao Kodali ,  Douglas Ele Martin ,  Harsh Dev Sharma

IPC分类号： G06F1900

CPC分类号： G06F9/38 ,  H03K19/0963 ,  H03K19/1735

摘要： A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.

摘要翻译： 提供了一种方法和装置，用于使得能够将多米诺骨牌电路转换成静态电路，而不需要重新设计芯片或集成电路掩模组。 多米诺骨牌电路掩模可以被设计为包括适当的额外的未连接的设备，其可以通过仅改变互连掩模而在芯片设计释放之后被添加或连接到电路中。 备用器件可以添加并选择性地用于使多米诺骨电路金属掩模可编程成逻辑等效的静态电路。 在第一示例性方法中，添加额外的设备，和/或将现有设备重新连接在多米诺骨牌电路中以形成互补的等效静态门。 在第二示例性方法中，使用电路中已经可用的设备并修改其电路连接，将多米诺骨电路转换成伪NMOS电路。

公开(公告)号：US5748028A

公开(公告)日：1998-05-05

申请号：US741731

申请日：1996-10-31

申请人： Douglas Ele Martin

发明人： Douglas Ele Martin

IPC分类号： H03K19/017 ,  H03K19/094 ,  H03K17/04

CPC分类号： H03K19/09425 ,  H03K19/01721

摘要： The invention is embodied in a receiver and a method for responding to an input signal. The input signal is received in a first stage of the receiver, which generates a first stage output signal responsive thereto. If the input signal does not exceed a first level, the first stage output signal is generated by an overvoltage element. That is, for this case, the overvoltage element passes the input signal through to the first stage output, and the first stage output voltage is not increased by a first stage pullup element. If, on the other hand, the input signal exceeds the first level, the first stage output signal voltage level is increased by the first stage pullup element to a higher output voltage level. The output signal from the first stage is received in a second stage. The second stage generates a second stage output responsive thereto. A second stage pullup element may be disabled by a mode signal in expectation that the input signal will exceed the first level, so that the first stage output voltage will not be increased by the second stage pullup element.

摘要翻译： 本发明体现在接收机和用于响应输入信号的方法中。 输入信号在接收机的第一级接收，其响应于此产生第一级输出信号。 如果输入信号不超过第一电平，则第一级输出信号由过电压元件产生。 也就是说，在这种情况下，过电压元件将输入信号传递到第一级输出，并且第一级上拉元件不会增加第一级输出电压。 另一方面，如果输入信号超过第一电平，则第一级上拉元件将第一级输出信号电压电平增加到更高的输出电压电平。 来自第一级的输出信号在第二级中被接收。 第二级产生响应于此的第二级输出。 第二级上拉元件可以由模式信号禁止，期望输入信号将超过第一级，使得第一级上拉元件不会增加第一级输出电压。

公开(公告)号：US5739700A

公开(公告)日：1998-04-14

申请号：US709706

申请日：1996-09-09

申请人： Douglas Ele Martin

发明人： Douglas Ele Martin

IPC分类号： H03K19/0185

CPC分类号： H03K19/018521

摘要： A method and apparatus is disclosed for outputting a signal responsive to, and shifted in signal level relative to, an input signal level. A driver includes first circuitry outputting a first signal responsive to an input signal, and second circuitry outputting a second signal responsive to the input signal. The first circuitry includes circuitry for substantially shifting the first signal level relative to the input signal and responds more slowly than the second circuitry. The driver output is responsive to both the first and second signals so that the second circuitry improves driver response.

摘要翻译： 公开了一种用于输出响应于信号电平并相对于输入信号电平移位的信号的方法和装置。 驱动器包括响应于输入信号输出第一信号的第一电路，以及响应于输入信号输出第二信号的第二电路。 第一电路包括用于相对于输入信号基本上移动第一信号电平并且比第二电路响应得更慢的电路。 驱动器输出响应第一和第二信号，使得第二电路改善驱动器响应。

公开(公告)号：US6084432A

公开(公告)日：2000-07-04

申请号：US050162

申请日：1998-03-30

申请人： Daniel Mark Dreps ,  Douglas Ele Martin

发明人： Daniel Mark Dreps ,  Douglas Ele Martin

IPC分类号： H03K17/16 ,  H03K19/175

CPC分类号： H03K17/164 ,  H03K17/163

摘要： A driver circuit has an output node coupled to a chip pad. A first PFET and a first resistor are connected between a power supply and the output node, wherein the first resistor is connected between the first PFET and the output node. A first NFET and a second resistor are connected between a ground potential and the output node, wherein the second resistor is connected between the first NFET and the output node. A third resistor is connected between an input to the driver circuit and a gate electrode of the first PFET. A fourth resistor is connected between the input to the driver circuit and a gate electrode of the first NFET. The pre-drive circuitry for driving the input to the PFET may include an NFET coupled between the ground potential and the input, wherein the gate electrode of the NFET receives the data signal to be driven. The NFET pre-drive circuitry may include a PFET coupled between the power supply and the input to the NFET portion of the driver circuit, wherein the gate electrode of this PFET also receives the data signal to be driven. A plurality of these driver circuits may be connected in parallel and in series in order to modify the output impedance.

摘要翻译： 驱动器电路具有耦合到芯片焊盘的输出节点。 第一PFET和第一电阻器连接在电源和输出节点之间，其中第一电阻连接在第一PFET和输出节点之间。 第一NFET和第二电阻器连接在接地电位和输出节点之间，其中第二电阻器连接在第一NFET与输出节点之间。 第三电阻器连接在驱动电路的输入端和第一PFET的栅电极之间。 在驱动电路的输入端与第一NFET的栅电极之间连接第四电阻。 用于驱动输入到PFET的预驱动电路可以包括耦合在地电位和输入端之间的NFET，其中NFET的栅电极接收待驱动的数据信号。 NFET预驱动电路可以包括耦合在电源和驱动电路的NFET部分的输入之间的PFET，其中该PFET的栅电极还接收待驱动的数据信号。 多个这些驱动器电路可并联并串联连接，以便修改输出阻抗。

公开(公告)号：US5818280A

公开(公告)日：1998-10-06

申请号：US570042

申请日：1995-12-11

申请人： Douglas Ele Martin

发明人： Douglas Ele Martin

IPC分类号： H03K19/0185 ,  H03K17/04

CPC分类号： H03K19/018521

摘要： A shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to switches in logic state of the input signal and whose voltage level is shifted with respect to the input signal. A feedback circuit feeds a signal derived from the output signal back to the shifter to precondition the shifter so that the speed of the output signal switching is accelerated.

摘要翻译： 移位器接收多逻辑状态输入信号，并且响应于输入信号的逻辑状态中的开关并且相对于输入信号偏移其电压电平而产生多逻辑状态输出信号。 反馈电路将从输出信号导出的信号反馈给移位器，以预调整移位器，从而加速输出信号切换的速度。

公开(公告)号：US5717355A

公开(公告)日：1998-02-10

申请号：US570043

申请日：1995-12-11

申请人： Douglas Ele Martin

发明人： Douglas Ele Martin

IPC分类号： H03K19/017 ,  H03K19/0185 ,  H03K17/04

CPC分类号： H03K19/018521 ,  H03K19/01707

摘要： In a method and apparatus for shifting the level of a signal a shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to changes in logic state of input signal and whose voltage level is shifted with respect to the input signal. The logic low state of the output signal is shifted to a certain voltage level above ground. A first switching device sets the voltage level of the logic low state. A feedback circuit feeds a signal derived from the output signal back to the switching device to precondition the shifter so that the speed of the output signal transition from one state to another is accelerated.

摘要翻译： 在用于移动信号电平的方法和装置中，移位器接收多逻辑状态输入信号，并响应于输入信号的逻辑状态的变化产生多逻辑状态输出信号，并且其电压电平相对于 输入信号。 输出信号的逻辑低电平状态转移到地面以上的一定电压电平。 第一开关器件设置逻辑低电平的电平。 反馈电路将从输出信号导出的信号反馈给开关装置，以预调整移位器，使得输出信号从一个状态转变到另一个状态的速度被加速。