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公开(公告)号：US06208907B1
公开(公告)日：2001-03-27
申请号：US09016653
申请日：1998-01-30
IPC分类号： G06F1900
CPC分类号： G06F9/38 , H03K19/0963 , H03K19/1735
摘要： A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.
摘要翻译： 提供了一种方法和装置，用于使得能够将多米诺骨牌电路转换成静态电路，而不需要重新设计芯片或集成电路掩模组。 多米诺骨牌电路掩模可以被设计为包括适当的额外的未连接的设备，其可以通过仅改变互连掩模而在芯片设计释放之后被添加或连接到电路中。 备用器件可以添加并选择性地用于使多米诺骨电路金属掩模可编程成逻辑等效的静态电路。 在第一示例性方法中，添加额外的设备，和/或将现有设备重新连接在多米诺骨牌电路中以形成互补的等效静态门。 在第二示例性方法中，使用电路中已经可用的设备并修改其电路连接，将多米诺骨电路转换成伪NMOS电路。
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2.发明授权Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs 失效减少功率动态逻辑电路，抑制稳定输入的重新评估
公开(公告)号：US6037804A
公开(公告)日：2000-03-14
申请号：US049741
申请日：1998-03-27
申请人： Christopher McCall Durham , Visweswara Rao Kodali , Michael Ju Hyeok Lee , Douglas Ele Martin , Harsh Dev Sharma
发明人： Christopher McCall Durham , Visweswara Rao Kodali , Michael Ju Hyeok Lee , Douglas Ele Martin , Harsh Dev Sharma
IPC分类号： H03K19/00 , H03K19/096 , H03K19/094
CPC分类号： H03K19/096 , H03K19/0016
摘要： A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.
摘要翻译： 降低功率的集成电路包括电路数据输入，电路数据输出和至少一行动态逻辑。 动态逻辑行包括行时钟输入，行数据输入和耦合到电路数据输出的行数据输出，其中根据电路数据输入的值导出在行数据输入处接收的值。 集成电路还包括比较器，其比较电路数据输入端的当前值和先前值，以及开关，其选择性地将在行时钟输入处接收的行时钟信号设置为非活动状态，并将行时钟信号暂时保持在非活动状态 对比较器的响应检测到电路数据输入端的当前先前值是等效的。 因此，动态逻辑行（并不需要）重新评估电路数据输入值，并降低功耗。
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公开(公告)号：US6107852A
公开(公告)日：2000-08-22
申请号：US81001
申请日：1998-05-19
CPC分类号： H03K3/012 , H03K3/356156
摘要： A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.
摘要翻译： 公开了一种用于减少与用于在数据处理系统中实现集成电路的电路中插入锁存相关联的惩罚的方法和装置。 公开了一种半导体器件，其包括主锁存电路，反馈锁存电路和输出端子。 主锁存电路能够接收输入数据信号和输入时钟信号。 主锁存电路根据输入数据和时钟信号产生锁存输出信号。 反馈锁存电路能够接收来自主锁存电路的锁存输出信号并存储锁存器输出信号。 反馈锁存电路能够产生由主锁存电路接收的反馈锁存电路输出信号，以维持锁存输出信号。 设备的输出端耦合到反馈锁存电路，用于输出等于反馈锁存电路输出信号的器件输出信号。
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4.发明授权Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets 失效物理设计技术在单个设计周期中提供单核和多核微处理器芯片，并使用共享掩模集提供制造批次公开(公告)号：US06406980B1
公开(公告)日：2002-06-18
申请号：US09645155
申请日：2000-08-24
IPC分类号： H01L21301
CPC分类号： H01L27/0207 , H01L27/118
摘要： A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.
摘要翻译： 提供了使用单个用于晶片的掩模的然后在所期望的芯片类型的时候产生多个集成芯片类型的晶片设计布局和方法，使用几个定制步骤来产生最终的集成芯片。 在一个实施例中，晶片布局包括多个组件分组和多个分割通道，每个分组通道将组件中的每一个与其他部件分离。 在选择了期望的特定类型的集成电路芯片之后，晶片可以处理最后几个层，并且使用用于集成电路芯片的合适的切割通道去除芯片。
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公开(公告)号：US6133758A
公开(公告)日：2000-10-17
申请号：US86737
申请日：1998-05-29
IPC分类号： G06F9/38 , H03K19/096 , H03K19/00
CPC分类号： H03K19/0966 , G06F9/3869
摘要： A method and apparatus is provided for changing a self-timed circuit into a self-resetting circuit to reduce the inherent delay of the self-timed circuit by an amount of latency between the assertion of the data and the assertion of the valid signal. Circuitry is provided to enable the effective de-coupling of the self-timing operation to enable data to move through the logic circuitry without the latency associated with the reception and generation of "valid" and "complete" signals being necessary. On the "receiving" side (the circuit being set into self-resetting mode), the logic circuit does not have to wait for the reception of the "valid" signals to begin operation. On the "driving" side (the circuit sending the data), the logic circuit does not have to wait for the "completion" signal to arrive to permit a new operation to occur.
摘要翻译： 提供了一种方法和装置，用于将自定时电路改变为自复位电路，以便将自定时电路的固有延迟减小在数据的断言和有效信号的断言之间的等待时间量。 提供电路以实现自定时操作的有效解耦，使得数据能够通过逻辑电路移动，而不需要与接收相关联的等待时间并产生“有效”和“完整”信号。 在“接收”侧（电路被设置为自复位模式）中，逻辑电路不必等待接收“有效”信号开始运行。 在“驱动”侧（发送数据的电路）中，逻辑电路不必等待“完成”信号到达以允许发生新的操作。
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公开(公告)号：US5896059A
公开(公告)日：1999-04-20
申请号：US854224
申请日：1997-05-09
IPC分类号： H03K19/003 , H03K3/01
CPC分类号： H03K19/003
摘要： An apparatus to remove from operation a decoupling capacitor connected to a power supply providing power to logic circuitry in an integrated circuit. One technique for doing so is to connect a fuse in series with a decoupling capacitor. The present invention amplifies current transmitting through the fuse in a positive feedback manner to force the fuse to blow sooner than would normally occur. Therefore, when the current through the decoupling capacitor is deemed unacceptable, the fuse current is increased until such a time that the fuse opens.
摘要翻译： 一种用于从操作中去除连接到向集成电路中的逻辑电路提供电力的电源的去耦电容器的装置。 一种这样做的技术是将保险丝与去耦电容串联。 本发明以正反馈方式放大通过保险丝传输的电流，以使熔丝比通常发生的更快地吹动。 因此，当通过去耦电容器的电流被认为是不可接受的时候，熔丝电流增加直至熔丝开启的时间为止。
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7.发明授权公开(公告)号：US06785826B1
公开(公告)日：2004-08-31
申请号：US08682471
申请日：1996-07-17
IPC分类号： G06F126
CPC分类号： G06F1/3203
摘要： A method and apparatus for reducing power dissipation within a functional unit of a microprocessor includes a power sensing circuit for sensing power dissipation of the functional unit. A low power mode identifying circuit identifies when the measured power dissipation of the functional unit exceeds a predetermined amount or value. Upon such a condition, a low power mode circuit operates the functional unit in a low power mode thereby reducing its power dissipation. Operation of the functional unit in the low power mode continues until the power dissipation reaches a safe level. The functional unit internally determines power dissipation and selectively enters a low power mode to reduce power dissipation of the functional unit. Low power mode operation of the functional unit reduces power dissipation of the functional unit.
摘要翻译： 一种用于降低微处理器的功能单元内功耗的方法和装置，包括用于感测功能单元的功耗的功率检测电路。 低功率模式识别电路识别功能单元的测量功耗何时超过预定量或值。 在这种情况下，低功率模式电路以低功率模式操作功能单元，从而降低其功耗。 低功耗模式下的功能单元的运行持续到功耗达到安全水平。 功能单元内部确定功耗，并选择性地进入低功耗模式以降低功能单元的功耗。 功能单元的低功耗模式操作降低了功能单元的功耗。
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公开(公告)号：US06522170B1
公开(公告)日：2003-02-18
申请号：US09067153
申请日：1998-04-27
IPC分类号： H03K1900
CPC分类号： H03K19/0966
摘要： A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.
摘要翻译： 已经发明了一种自定时CMOS静态电路技术，其提供了对源电路的完全握手; 通过互锁内部和外部信号来防止输入数据丢失; 电路和接收器之间完全握手自定时电路; 借助于输出数据信息的内部锁定来防止丢失的访问操作信息; 以及一些类型的动态自定时系统的插件兼容性。 整个系统的最终结果是现在可以使用静态CMOS电路来生成自定时系统。 这与依赖于动态电路的现有自定时系统形成对比。 因此，可以保持静态电路的质量并充分利用它们。
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公开(公告)号：US06285217B1
公开(公告)日：2001-09-04
申请号：US09391423
申请日：1999-09-08
IPC分类号： H03K19096
CPC分类号： G11C7/065
摘要： Dynamic logic circuits with reduced evaluation time provide faster output in dynamically evaluating logic circuits by increasing the rate of change of the voltage at the junction of logic input ladders. The circuits use a cross-coupled amplifier to charge the input ladder combining node once the node begins to evaluate.
摘要翻译： 具有减少评估时间的动态逻辑电路通过提高逻辑输入梯级的连接点处的电压变化率，在动态评估逻辑电路方面提供更快的输出。 一旦节点开始评估，这些电路使用交叉耦合放大器对输入梯形图组合节点进行充电。
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10.发明授权Method and system for determining which memory locations have been accessed in a self timed cache architecture 失效用于确定在自定时高速缓存结构中已经访问了哪些存储器位置的方法和系统
公开(公告)号：US6115789A
公开(公告)日：2000-09-05
申请号：US845868
申请日：1997-04-28
CPC分类号： G11C29/32
摘要： The present invention provides a method and system for providing observability of memory address access for self-timed cache designs. A system according to the present invention for determining which memory location has been accessed in a self-timed cache comprises a content addressable memory; a secondary memory coupled to the content addressable memory, wherein the secondary memory includes at least one memory location which may be selected by the content addressable memory based upon a self-timed cache access. The system further includes a test circuitry coupled to the content addressable memory, wherein the test circuitry stores a pointer which points to a selected memory location in response to the self-timed cache access of the secondary memory.
摘要翻译： 本发明提供了一种用于提供用于自定时高速缓存设计的存储器地址访问的可观察性的方法和系统。 根据本发明的用于确定在自定时高速缓存中已经访问了哪个存储器位置的系统包括内容可寻址存储器; 耦合到内容可寻址存储器的辅助存储器，其中辅存储器包括可以由内容可寻址存储器基于自定时高速缓存访问来选择的至少一个存储器位置。 系统还包括耦合到内容可寻址存储器的测试电路，其中测试电路响应于辅助存储器的自定时高速缓存访问而存储指向所选存储器位置的指针。
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