-
公开(公告)号：US5453957A
公开(公告)日：1995-09-26
申请号：US123377
申请日：1993-09-17
CPC分类号： G11C8/04 , G11C7/1018 , G11C7/1042
摘要： The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable. A particular embodiment for generating an aligned sequential burst address sequence is described.
摘要翻译： 使用交错存储器阵列的突发模式存储器架构为偶数和奇数EPROM阵列提供偶数阵列中存储偶数地址的数据和奇数阵列中存储奇数地址的数据。 控制电路从存储器系统控制器接收初始地址，然后在包含初始地址的脉冲串地址空间内从偶数和奇数列中访问所有数据。 一对异相计数器分别产生用于访问偶数和奇数数组的偶数和奇数地址。 每个计数器依次递增地址，直到达到突发地址空间边界，然后计数器循环到突发地址空间的开头，以在突发地址空间内生成任何剩余的地址。 突发模式控制电路能够处理各种突发排序模式。 突发地址空间大小和突发排序模式是可选择的。 描述了用于生成对准的连续突发地址序列的特定实施例。
-
公开(公告)号：US5381370A
公开(公告)日：1995-01-10
申请号：US111164
申请日：1993-08-24
CPC分类号： G11C29/84
摘要： A memory is described that includes a main memory array having a plurality of main memory locations and a redundant memory array having a plurality of redundant memory locations. A main decoding circuit is coupled to the main memory array for decoding an address received from an external circuit to access a selected one of the plurality of main memory locations. A storage circuit is provided for pre-storing the address of the selected one of the plurality of main memory locations when the selected one of the plurality of main memory locations is defective. A redundant comparison circuit is coupled to the redundant memory array and the storage circuit for comparing the external address with the address stored in the storage circuit in order to access a selected one of the plurality of redundant memory locations. A static decoding circuit is coupled to the storage circuit and the main select circuit for decoding the address received from the storage circuit and for disabling the main select circuit from accessing the selected one of the plurality of main memory locations such that when the redundant comparison circuit accesses the selected one of the plurality of redundant memory locations, the main select circuit has already been disabled from accessing the selected one of the plurality of main memory locations.
摘要翻译： 描述了包括具有多个主存储器位置的主存储器阵列和具有多个冗余存储器位置的冗余存储器阵列的存储器。 主解码电路耦合到主存储器阵列，用于对从外部电路接收的地址进行解码以访问多个主存储器位置中的所选择的一个。 提供一种存储电路，用于当所述多个主存储器位置中的所选择的一个主存储器位置有缺陷时，预先存储多个主存储器位置中所选择的一个的地址。 冗余比较电路耦合到冗余存储器阵列和存储电路，用于将外部地址与存储在存储电路中的地址进行比较，以便访问多个冗余存储器位置中的所选择的一个。 静态解码电路耦合到存储电路和主选择电路，用于解码从存储电路接收的地址，并禁止主选择电路访问多个主存储器位置中的所选择的一个，使得当冗余比较电路 访问所述多个冗余存储器位置中的所选择的一个，所述主选择电路已经被禁用以访问所述多个主存储器位置中的所选择的一个。
-
公开(公告)号：US5831926A
公开(公告)日：1998-11-03
申请号：US473076
申请日：1995-06-07
CPC分类号： G11C8/04 , G11C7/1018 , G11C7/1042
摘要： The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable. A particular embodiment for generating an aligned sequential burst address sequence is described.
-
公开(公告)号：US5787047A
公开(公告)日：1998-07-28
申请号：US745876
申请日：1996-11-08
CPC分类号： G11C8/04 , G11C7/1018 , G11C7/1042
摘要： The burst mode memory architecture using interleaved memory arrays provides even and odd EPROM arrays with data having even addresses stored in the even array and data having odd addresses stored in the odd array. A control circuit receives an initial address from a memory system controller and then accesses all data from the even and odd arrays within a burst address space containing the initial address. A pair of out-of-phase counters generate even and odd addresses, respectively, for accessing the even and odd arrays. Each counter increments addresses sequentially until a burst address space boundary is reached, then the counters wrap around to a beginning of a burst address space to generate any remaining addresses within a burst address space. The burst mode control circuitry is capable of processing a variety of burst sequencing modes. The burst address space size and the burst sequencing mode are selectable. A particular embodiment for generating an aligned sequential burst address sequence is described.
-
5.发明授权High voltage reference and measurement circuit for verifying a programmable cell 失效用于验证可编程单元的高电压参考和测量电路
公开(公告)号：US5710778A
公开(公告)日：1998-01-20
申请号：US625332
申请日：1996-04-01
申请人： Roger J. Bettman , S. Babar Raza , Donald Yu , Donald A. Krall , Anita X. Meng , Christopher S. Norris
发明人： Roger J. Bettman , S. Babar Raza , Donald Yu , Donald A. Krall , Anita X. Meng , Christopher S. Norris
CPC分类号： G11C29/021 , G11C29/02 , G11C29/028 , G11C29/50 , G11C29/52 , G11C16/04 , G11C2029/5004
摘要： The present invention provides a circuit for supplying a verifying reference and measurement voltage for use in verifying the programming of a programmable cell. The present invention provides the verifying reference and measurement voltage through internal circuitry on the cell and eliminate any requirement for an externally provided reference voltage. The verifying voltage is provided by modifying the programming voltage. The programming voltage is stepped down or stepped up through the use of internal circuitry to provide the reference and measurement voltage.
摘要翻译： 本发明提供一种用于提供用于验证可编程单元的编程的验证参考和测量电压的电路。 本发明通过电池上的内部电路提供验证参考和测量电压，并且消除对外部提供的参考电压的任何要求。 通过修改编程电压来提供验证电压。 编程电压通过使用内部电路进行降压或升压，以提供参考电压和测量电压。
-
公开(公告)号：US5760438A
公开(公告)日：1998-06-02
申请号：US800656
申请日：1997-02-04
IPC分类号： G11C16/04 , H01L27/115 , H01L29/788
CPC分类号： G11C16/0441 , H01L27/115 , H01L29/7881 , H01L29/7883
摘要： A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts. The erase node includes a buried N+ drain region in a P-type substrate, a buried implant plate doped N-type adjacent the drain region in the substrate, a tunnel oxide disposed over at least a portion of the plate and the drain region, the tunnel oxide extending into and abutting a gate oxide region, and thence to a field oxide region in a relaxed fashion, a polycrystalline silicon floating gate disposed over the field oxide, gate oxide, and tunnel oxide regions, a sandwich of ONO on the floating gate, and a polycrystalline silicon control gate (poly 2) disposed on the ONO. Programming occurs through the programming transistor. Reading occurs through a read path including the read transistor. During programming, coupling is improved at the gate of the programming transistor by an erase node boosting technique. This technique involves applying a relatively "boosted" voltage level to the drain region of the erase node which reduces the backbias threshold effect of erase node capacitors. Similarly, during a read operation, a relatively "boosted" voltage is applied to the drain region of the erase node, which, by way of the buried implant plate, reduces the backbias threshold effect of the erase node capacitors wherein coupling at the control gate of the read transistor is improved.
摘要翻译： 快速的无场闪存单元包括具有控制栅极和浮动栅极的擦除节点，两者都由多晶硅形成，共享浮动栅极的编程晶体管和与擦除节点的控制栅极以及共享浮置栅极的读取晶体管， 控制门与擦除节点和程序晶体管。 本发明的存储单元适用于子5 nS范围（2-5 nS）的快速可编程逻辑器件（PLD）以及其他逻辑和存储器部件。 擦除节点包括P型衬底中的掩埋N +漏极区域，与衬底中的漏极区域相邻的N型掺杂的埋入式植入板，设置在板和漏极区域的至少一部分上的隧道氧化物， 隧道氧化物延伸到栅极氧化物区域中并邻接栅氧化物区域，从而以弛豫方式延伸到场氧化物区域;多晶硅浮置栅极，设置在场氧化物，栅极氧化物和隧道氧化物区域上，在浮置栅极上的ONO的夹层 ，以及设置在ONO上的多晶硅控制栅（poly 2）。 通过编程晶体管进行编程。 通过包括读取晶体管的读取路径进行读取。 在编程期间，通过擦除节点升压技术在编程晶体管的栅极处改善耦合。 该技术涉及将相对“升压的”电压电平施加到擦除节点的漏极区域，这降低了擦除节点电容器的反向阈值效应。 类似地，在读取操作期间，相对“升压”的电压被施加到擦除节点的漏极区域，该漏极区域通过掩埋的注入板减小擦除节点电容器的反向阈值效应，其中在控制门 的读取晶体管。
-
公开(公告)号：US5648669A
公开(公告)日：1997-07-15
申请号：US452217
申请日：1995-05-26
IPC分类号： G11C16/04 , H01L27/115 , H01L29/788 , H01L29/76
CPC分类号： G11C16/0441 , H01L27/115 , H01L29/7881 , H01L29/7883
摘要： A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharing the floating gate and control gate with the erase node and program transistor. The inventive memory cell is suitable for use in fast Programmable Logic Devices (PLDs) in the sub 5 nS range (2-5 nS), and other logic and memory parts. The erase node includes a buried N+ drain region in a P-type substrate, a buried implant plate doped N-type adjacent the drain region in the substrate, a tunnel oxide disposed over at least a portion of the plate and the drain region, the tunnel oxide extending into and abutting a gate oxide region, and thence to a field oxide region in a relaxed fashion, a polycrystalline silicon floating gate disposed over the field oxide, gate oxide, and tunnel oxide regions, a sandwich of ONO on the floating gate, and a polycrystalline silicon control gate (poly 2) disposed on the ONO. Programming occurs through the programming transistor. Reading occurs through a read path including the read transistor. During programming, coupling is improved at the gate of the programming transistor by an erase node boosting technique. This technique involves applying a relatively "boosted" voltage level to the drain region of the erase node which reduces the backbias threshold effect of erase node capacitors. Similarly, during a read operation, a relatively "boosted" voltage is applied to the drain region of the erase node, which, by way of the buried implant plate, reduces the backbias threshold effect of the erase node capacitors wherein coupling at the control gate of the read transistor is improved.
摘要翻译： 快速的无场闪存单元包括具有控制栅极和浮动栅极的擦除节点，两者都由多晶硅形成，共享浮动栅极的编程晶体管和与擦除节点的控制栅极以及共享浮置栅极的读取晶体管， 控制门与擦除节点和程序晶体管。 本发明的存储单元适用于子5 nS范围（2-5 nS）的快速可编程逻辑器件（PLD）以及其他逻辑和存储器部件。 擦除节点包括P型衬底中的掩埋N +漏极区域，与衬底中的漏极区域相邻的N型掺杂的埋入式植入板，设置在板和漏极区域的至少一部分上的隧道氧化物， 隧道氧化物延伸到栅极氧化物区域中并邻接栅氧化物区域，从而以弛豫方式延伸到场氧化物区域;多晶硅浮置栅极，设置在场氧化物，栅极氧化物和隧道氧化物区域上，在浮置栅极上的ONO的夹层 ，以及设置在ONO上的多晶硅控制栅（poly 2）。 通过编程晶体管进行编程。 通过包括读取晶体管的读取路径进行读取。 在编程期间，通过擦除节点升压技术在编程晶体管的栅极处改善耦合。 该技术涉及将相对“升压的”电压电平施加到擦除节点的漏极区域，这降低了擦除节点电容器的反向阈值效应。 类似地，在读取操作期间，相对“升压”的电压被施加到擦除节点的漏极区域，该漏极区域通过掩埋的注入板减小擦除节点电容器的反向阈值效应，其中在控制门 的读取晶体管。
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.018 秒)
