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公开(公告)号：US20070186045A1
公开(公告)日：2007-08-09
申请号：US10897474
申请日：2004-07-23
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/0811 , G06F12/0897
摘要： A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the potential impact to other cache levels within the cache hierarchy.
摘要翻译： 一种用于智能驱逐包含缓存架构内的高速缓存行的技术。 更具体地，本发明的实施例涉及一种基于对高速缓存层级内的其他高速缓存级别的潜在影响来驱逐包容性高速缓存层级内的高速缓存行的技术。
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公开(公告)号：US20060218352A1
公开(公告)日：2006-09-28
申请号：US11087916
申请日：2005-03-22
CPC分类号： G06F12/128 , G06F12/0811 , G06F12/0831
摘要： A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.
摘要翻译： 一种用于智能驱逐包含缓存架构内的高速缓存行的技术。 更具体地，本发明的实施例涉及一种基于在高级缓存和较低级别高速缓存之间生成的高速缓存一致性流量来驱逐包容性高速缓存层级内的高速缓存行的技术。
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公开(公告)号：US20130179716A1
公开(公告)日：2013-07-11
申请号：US13780052
申请日：2013-02-28
申请人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
发明人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F13/4022 , Y02D10/126
摘要： In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。 该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。 除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。 该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。 描述和要求保护其他实施例。
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公开(公告)号：US20130080795A1
公开(公告)日：2013-03-28
申请号：US13247594
申请日：2011-09-28
申请人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
发明人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F13/4022 , Y02D10/126
摘要： In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
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公开(公告)号：US08275942B2
公开(公告)日：2012-09-25
申请号：US11316560
申请日：2005-12-22
CPC分类号： G06F12/0842
摘要： According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.
摘要翻译： 根据本发明的一个实施例，公开了一种用于选择高速缓存中的多个高速缓存路径的第一子集的方法，用于存储被识别为高优先级硬件线程的硬件线程，以用于与高速缓存通信的多线程处理器进行处理; 将高优先级的硬件线程分配给所选择的第一子集; 监视分配给所选择的多个高速缓存路线的第一子集的高优先级硬件线程的高速缓存使用; 以及如果所述高优先级硬件线程的高速缓存使用基于所述监视超过预定的非活动高速缓存使用阈值，则将所分配的高优先级硬件线程重新分配给所述多个高速缓存路径中的任何高速缓存方式。
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6.发明授权Method, apparatus, and a system for dynamically configuring a prefetcher based on a thread specific latency metric 有权方法，装置和用于基于线程特定的等待时间度量动态配置预取器的系统公开(公告)号：US08079031B2
公开(公告)日：2011-12-13
申请号：US11256536
申请日：2005-10-21
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/383 , G06F12/0862 , G06F2212/502
摘要： A discussion of a dynamic configuration for a prefetcher is proposed. For example, a thread specific latency metric is calculated and provides dynamic feedback to the software on a per thread basis via the configuration and status registers. Likewise, the software can optionally use the information from the registers to dynamically configure the prefetching behavior and allows the software to be able to both query the performance and configure the prefetcher.
摘要翻译： 提出了对预取器的动态配置的讨论。 例如，计算线程特定的延迟度量，并通过配置和状态寄存器在每个线程的基础上向软件提供动态反馈。 同样，软件可以选择使用来自寄存器的信息来动态地配置预取行为，并允许软件能够查询性能并配置预取器。
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7.发明授权公开(公告)号：US07711901B2
公开(公告)日：2010-05-04
申请号：US10779204
申请日：2004-02-13
CPC分类号： G06F12/128
摘要： A cache line replacement protocol for selecting a cache line for replacement based at least in part on the inter-cache traffic generated as a result of the cache line being replaced.
摘要翻译： 用于至少部分地基于作为高速缓存行被替换的结果生成的高速缓存间流量来选择用于替换的高速缓存行的高速缓存行替换协议。
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公开(公告)号：US20070150657A1
公开(公告)日：2007-06-28
申请号：US11316560
申请日：2005-12-22
IPC分类号： G06F12/00
CPC分类号： G06F12/0842
摘要： According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.
摘要翻译： 根据本发明的一个实施例，公开了一种用于选择高速缓存中的多个高速缓存路径的第一子集的方法，用于存储被识别为高优先级硬件线程的硬件线程，以用于与高速缓存通信的多线程处理器进行处理; 将高优先级的硬件线程分配给所选择的第一子集; 监视分配给所选择的多个高速缓存路线的第一子集的高优先级硬件线程的高速缓存使用; 以及如果所述高优先级硬件线程的高速缓存使用基于所述监视超过预定的非活动高速缓存使用阈值，则将所分配的高优先级硬件线程重新分配给所述多个高速缓存路径中的任何高速缓存方式。
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9.发明授权Dynamically adjusting power of non-core processor circuitry including buffer circuitry 有权动态调整包括缓冲电路在内的非核心处理器电路的功率公开(公告)号：US08914650B2
公开(公告)日：2014-12-16
申请号：US13247594
申请日：2011-09-28
申请人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
发明人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
CPC分类号： G06F1/324 , G06F13/4022 , Y02D10/126
摘要： In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。 该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。 除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。 该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。 描述和要求保护其他实施例。
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公开(公告)号：US07277992B2
公开(公告)日：2007-10-02
申请号：US11087916
申请日：2005-03-22
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/0811 , G06F12/0831
摘要： A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.
摘要翻译： 一种用于智能驱逐包含缓存架构内的高速缓存行的技术。 更具体地，本发明的实施例涉及一种基于在高级缓存和较低级别高速缓存之间生成的高速缓存一致性流量来驱逐包容性高速缓存层级内的高速缓存行的技术。
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