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1.发明申请公开(公告)号：US20070239966A1
公开(公告)日：2007-10-11
申请号：US11757166
申请日：2007-06-01
IPC分类号： G06F15/76
CPC分类号： G06F15/7832 , H04L49/109 , H04L49/602
摘要： A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.
摘要翻译： 一种片上系统（SoC）组件，其包括包括多个多个处理器的单个独立多处理器子系统核心，每个多处理器具有与其相关联的本地存储器形成处理器集群; 并且交换结构意味着连接SoC集成电路（IC）中的每个处理器集群。 当配置为DSP，协处理器，混合ASIC或网络处理安排时，单个SoC独立多处理器子系统内核能够对SoC设备执行多线程操作处理。 交换结构意味着另外将SoC本地系统总线设备与SoC处理器组件与独立的多处理器子系统核心互连。
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公开(公告)号：US20050021874A1
公开(公告)日：2005-01-27
申请号：US10768828
申请日：2004-01-30
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译： 一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行 在单个集成电路芯片内。 单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。 分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。 单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。
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3.发明申请公开(公告)号：US20050021871A1
公开(公告)日：2005-01-27
申请号：US10604491
申请日：2003-07-25
CPC分类号： G06F15/7832 , H04L49/109 , H04L49/602
摘要： A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.
摘要翻译： 一种片上系统（SoC）组件，其包括包括多个多个处理器的单个独立多处理器子系统核心，每个多处理器具有与其相关联的本地存储器形成处理器集群; 并且交换结构意味着连接SoC集成电路（IC）中的每个处理器集群。 当配置为DSP，协处理器，混合ASIC或网络处理安排时，单个SoC独立多处理器子系统内核能够对SoC设备执行多线程操作处理。 交换结构意味着另外将SoC本地系统总线设备与SoC处理器组件与独立的多处理器子系统核心互连。
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公开(公告)号：US20050008011A1
公开(公告)日：2005-01-13
申请号：US10604295
申请日：2003-07-09
IPC分类号： H04L12/56
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9052
摘要： A method and system is provided to efficiently manage memory in a network device that receives packets of variable size. The memory is allocated into portions whereby each portion, comprising multiple equally-sized buffers, receives packets of a particular size. One portion is used for smaller packet sizes and another portion is for larger packet sizes, although other portions may be created. As packets are received at the network device, they are stored into the appropriate memory portion based on their size. The number of available buffers in each portion is monitored so that, when it falls below a threshold, buffers are reallocated to the other thereby increasing the overall memory efficiency.
摘要翻译： 提供了一种方法和系统来有效地管理接收可变大小的分组的网络设备中的存储器。 存储器被分配到部分，由此包括多个相等大小的缓冲器的每个部分接收特定大小的分组。 一部分用于较小的分组大小，另一部分用于较大的分组大小，但可以创建其他部分。 当在网络设备处接收到分组时，它们基于它们的大小被存储到适当的存储器部分中。 监视每个部分中的可用缓冲器的数量，使得当其低于阈值时，缓冲器被重新分配到另一个，从而增加总体存储器效率。
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公开(公告)号：US20050025152A1
公开(公告)日：2005-02-03
申请号：US10604557
申请日：2003-07-30
摘要： A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.
摘要翻译： 提供了一种方法和系统来有效地排序通过网络接收的分组。 该方法通过检测失序分组来检测一个或多个分组流的序列中断，并且将顺序分组的分段进入用于特定流的单独的存储区域，例如链表。 传输队列和重排序表用于记录每个段的起始序列号。 参考传输队列以定位从流的最低分组序列号开始的分段。 与段相关联的分组按顺序传输。 然后，重复地搜索传输队列用于相关联的分组链的传输的下一个最低分组序列号，直到传输队列被清空。
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公开(公告)号：US10078515B2
公开(公告)日：2018-09-18
申请号：US13251441
申请日：2011-10-03
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/30105 , G06F9/30127 , G06F9/30185 , G06F9/3832 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/462
摘要： Operand liveness state information is maintained during context switches for current architected operands of executing programs. The current operand state information indicates whether corresponding current operands are enabled or disabled for use by a first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands. A machine instruction of the first program module accesses a current operand by using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.
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公开(公告)号：US09727336B2
公开(公告)日：2017-08-08
申请号：US13234785
申请日：2011-09-16
CPC分类号： G06F9/3013 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016 , G06F9/30189
摘要： Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite register file, and therefore, different sets of functional units. At least one operand of the instruction specifies which set of registers, and therefore, which set of functional units, is to be used in performing the sub-function. The instruction can perform various functions (e.g., move, load, etc.) and a sub-function of the function specifies the type of function (e.g., move-floating point; move-vector; etc.).
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8.发明授权Prefix computer instruction for compatibily extending instruction functionality 有权前缀计算机指令，用于兼容扩展指令功能公开(公告)号：US09329869B2
公开(公告)日：2016-05-03
申请号：US13251426
申请日：2011-10-03
CPC分类号： G06F9/30145 , G06F9/30 , G06F9/30185 , G06F9/34 , G06F9/3826 , G06F9/384
摘要： A prefix instruction is executed and passes operands to a net instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a target register of the prefix instruction execution.
摘要翻译： 执行前缀指令并将操作数传递到网络指令而不将操作数存储在架构资源中，使得下一条指令的执行使用由前缀指令提供的操作数来执行操作，操作数可以是前缀指令立即字段或 前缀指令执行的目标寄存器。
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公开(公告)号：US09098408B2
公开(公告)日：2015-08-04
申请号：US13592578
申请日：2012-08-23
申请人： Ruchi Mahindru , Valentina Salapura
发明人： Ruchi Mahindru , Valentina Salapura
CPC分类号： G06F11/07 , G06F11/0709 , G06F11/0784 , G06F11/34 , G06Q10/103 , G06Q10/20
摘要： Consolidating problem tickets for a multi-tiered application may comprise identifying a plurality of correlated virtual machines that are running one or more application components of the multi-tiered application. Problem reports may be identified that are generated by one or more of the plurality of correlated virtual machines and caused by a failure of a same single component of the multi-tiered application. The identified problem reports may be consolidated into a single ticket and placed into a ticket handling system.
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公开(公告)号：US08904392B2
公开(公告)日：2014-12-02
申请号：US13484797
申请日：2012-05-31
申请人： George Chiu , Alan G. Gara , Valentina Salapura
发明人： George Chiu , Alan G. Gara , Valentina Salapura
CPC分类号： G06F11/348 , G06F11/3409 , G06F2201/86 , G06F2201/88 , Y02D10/34
摘要： A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.
摘要翻译： 用于监视在多处理器系统中发生的事件的性能的性能监视单元（PMU）和方法。 多处理器系统包括多个处理器设备单元，用于产生表示处理器设备中事件发生的信号的每个处理器设备，以及用于性能监控的单个共享计数器资源。 性能监视器单元由多处理器系统中的所有处理器核共享。 PMU进一步被编程为监视从非处理器设备发出的事件信号。
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