公开(公告)号：US06368908B1

公开(公告)日：2002-04-09

申请号：US09200242

申请日：1998-11-25

申请人： Chuan-Fu Wang ,  J. S. Jason Jenq

发明人： Chuan-Fu Wang ,  J. S. Jason Jenq

IPC分类号： H01L218234

CPC分类号： H01L28/87 ,  H01L28/91

摘要： A method of fabricating a capacitor includes formation of a stacked layer formed by alternately forming conductive layers and isolation layers and then patterning these layers to form a stacked layer. An opening is formed above the source/drain region. A conductive spacer is formed on the sidewall of the opening. The conductive spacer is used as a mask. The dielectric layer below the stacked layer exposed by the opening is removed to form a contact hole. The top isolation layer of the stacked layer is removed. A conductive layer is formed over the substrate to fill the contact hole. The conductive spacer is covered by the conductive layer to form a raised region. A stacked spacer is formed beside the raised region. The isolation spacers of the stacked spacer and the isolation layer are removed to expose a storage electrode.

摘要翻译： 制造电容器的方法包括形成通过交替地形成导电层和隔离层形成的堆叠层，然后对这些层进行图案化以形成堆叠层。 在源极/漏极区域上形成开口。 在开口的侧壁上形成导电间隔物。 导电间隔物用作掩模。 去除由开口暴露的堆叠层下方的电介质层，形成接触孔。 去除堆叠层的顶部隔离层。 在衬底上形成导电层以填充接触孔。 导电间隔物被导电层覆盖以形成凸起区域。 在凸起区域旁边形成层叠间隔物。 去除层叠间隔物和隔离层的隔离间隔物以暴露存储电极。

公开(公告)号：US06140201A

公开(公告)日：2000-10-31

申请号：US172407

申请日：1998-10-14

申请人： J. S. Jason Jenq ,  Sun-Chieh Chien ,  Der-Yuan Wu ,  Chuan-Fu Wang

发明人： J. S. Jason Jenq ,  Sun-Chieh Chien ,  Der-Yuan Wu ,  Chuan-Fu Wang

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/92 ,  H01L21/3143 ,  H01L27/10852

摘要： A method for fabricating a cylinder capacitor of a DRAM cell that starts with forming a first oxide layer and then a doped first polysilicon layer on a substrate, patterning the first polysilicon layer to form a first opening that exposes the first oxide layer, forming a polysilicon spacer at the laterals of the first opening. Then, a portion of the first oxide layer is removed to expose the substrate by using the polysilicon spacer and the first polysilicon layer as a mask. A doped second polysilicon layer is formed on the first polysilicon layer and in the first opening. A portion of the second polysilicon layer is removed to form a second opening. A oxide spacer is formed on the laterals of the second opening, and is used as mask to remove a portion of the second polysilicon layer for forming a lower electrode. A dielectric layer and then a third polysilicon layer are formed on the lower electrode after the silicon oxide spacer is removed, wherein the third polysilicon is an upper electrode.

摘要翻译： 一种用于制造DRAM单元的圆柱电容器的方法，其开始于形成第一氧化物层，然后在衬底上形成掺杂的第一多晶硅层，图案化第一多晶硅层以形成暴露第一氧化物层的第一开口，形成多晶硅 间隔在第一个开口的边缘。 然后，通过使用多晶硅间隔物和第一多晶硅层作为掩模，去除第一氧化物层的一部分以暴露衬底。 掺杂的第二多晶硅层形成在第一多晶硅层和第一开口中。 去除第二多晶硅层的一部分以形成第二开口。 在第二开口的侧壁上形成氧化物间隔物，并且用作掩模以去除用于形成下电极的第二多晶硅层的一部分。 在除去氧化硅间隔物之后，在下电极上形成电介质层，然后形成第三多晶硅层，其中第三多晶硅是上电极。

公开(公告)号：US6080621A

公开(公告)日：2000-06-27

申请号：US165253

申请日：1998-10-01

申请人： Chuan-Fu Wang ,  J. S. Jason Jenq

发明人： Chuan-Fu Wang ,  J. S. Jason Jenq

IPC分类号： H01L21/8242 ,  H01L21/8234 ,  H01L21/8249

CPC分类号： H01L27/10852

摘要： A method of forming a DRAM capacitor that utilizes cap layers and spacers to surround the gate and bit line so that the necessary contact openings in a DRAM can be formed in two self-aligned contact processing operations. The capacitor of the DRAM is fabricated by forming contact node and openings within an insulating layer above a substrate, and then forming a first conductive layer conformal to the surface profile of the substrate above the substrate structure. Next, spacers are formed on the sidewalls of the conductive layer, and then a second conductive layer is formed filling the spacer between the spacers and over the substrate structure. Thereafter, a portion of the first conductive layer and the second conductive layer is removed to expose the spacers and the insulating layer. Finally, the spacers and the insulating layer are removed to expose a lower electrode structure that comprises the first and the second conductive layers.

摘要翻译： 一种形成DRAM电容器的方法，该DRAM电容器利用盖层和隔离物围绕栅极和位线，使得可以在两个自对准的接触处理操作中形成DRAM中必需的接触开口。 通过在衬底上方的绝缘层内形成接触节点和开口，然后形成与衬底结构上方的衬底的表面轮廓一致的第一导电层来制造DRAM的电容器。 接下来，在导电层的侧壁上形成间隔物，然后形成第二导电层，填充间隔物之间​​的间隔物和衬底结构上。 此后，去除第一导电层和第二导电层的一部分以露出间隔物和绝缘层。 最后，去除间隔物和绝缘层以暴露包括第一和第二导电层的下电极结构。

公开(公告)号：US06303430B1

公开(公告)日：2001-10-16

申请号：US09186300

申请日：1998-11-04

申请人： J. S. Jason Jenq

发明人： J. S. Jason Jenq

IPC分类号： H01L218242

CPC分类号： H01L28/91 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/84

摘要： A method of manufacturing DRAM capacitor includes forming a tungsten plug to connect with the source/drain region of a silicon substrate and using tungsten to form the upper and lower electrodes of the capacitor. The tungsten lower electrode of this invention is formed by depositing tungsten over the substrate using a physical vapor deposition method, and then depositing tungsten again using a chemical vapor deposition method so that a roughened surface is produced. Consequently, the tungsten lower electrode has a greater surface area, thereby increasing the capacitance of the capacitor. In addition, tantalum pentoxide is used to form the dielectric layer. Since tantalum pentoxide has a high dielectric constant, the effective capacitance of the capacitor is further increased.

摘要翻译： 制造DRAM电容器的方法包括形成与硅衬底的源极/漏极区域连接的钨插塞并且使用钨以形成电容器的上部和下部电极。 本发明的钨下电极通过使用物理气相沉积法在基板上沉积钨形成，然后使用化学气相沉积法沉积钨，从而产生粗糙表面。 因此，钨下电极具有更大的表面积，从而增加电容器的电容。 此外，五氧化二钽用于形成电介质层。 由于五氧化二钽具有高介电常数，电容器的有效电容进一步增加。

公开(公告)号：US06169016A

公开(公告)日：2001-01-02

申请号：US09181302

申请日：1998-10-28

申请人： Sun-Chieh Chien ,  J. S. Jason Jenq

发明人： Sun-Chieh Chien ,  J. S. Jason Jenq

IPC分类号： H01L21425

CPC分类号： H01L21/28512 ,  H01L21/28525

摘要： A method of forming contacts is provided. A thin polysilicon layer with a thickness of about 200-400 Å is deposited after forming a contact opening in a substrate. Then, the polysilicon layer is heavily doped using ion implantation to increase the number of mobile carriers in the polysilicon and to destroy the thin oxide layer formed naturally on the substrate, which destruction enhances the contact between the substrate and the polysilicon. A thick polysilicon layer is deposited on the thin polysilicon to form a bit line contact and a node contact.

摘要翻译： 提供了形成触点的方法。 在衬底中形成接触开口之后，沉积厚度约为200-400埃的薄多晶硅层。 然后，使用离子注入对多晶硅层进行重掺杂，以增加多晶硅中的移动载流子的数量并破坏在衬底上自然形成的薄氧化层，这种破坏增强了衬底和多晶硅之间的接触。 厚多晶硅层沉积在薄多晶硅上以形成位线接触和节点接触。

公开(公告)号：US06211079B1

公开(公告)日：2001-04-03

申请号：US09164922

申请日：1998-10-01

申请人： J. S. Jason Jenq

发明人： J. S. Jason Jenq

IPC分类号： H01L2144

CPC分类号： H01L27/10894 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/84

摘要： A method for fabricating interconnects of a DRAM, in which the contact windows are formed segment by segment and the contact windows are filled segment by segment to form interconnects. Also, tungsten plugs are used to replace the polysilicon plugs and the polysilicon bit lines, so as to reduce the resistance and increase the operating speed.

摘要翻译： 一种用于制造DRAM的互连的方法，其中接触窗口逐段形成，接触窗口逐段填充以形成互连。 此外，钨插头用于替代多晶硅插头和多晶硅位线，以便降低电阻并提高工作速度。

公开(公告)号：US6051507A

公开(公告)日：2000-04-18

申请号：US172406

申请日：1998-10-14

申请人： J. S. Jason Jenq ,  Der-Yuan Wu

发明人： J. S. Jason Jenq ,  Der-Yuan Wu

IPC分类号： H01L21/02 ,  H01L21/00

CPC分类号： H01L28/82 ,  H01L28/84 ,  H01L28/92

摘要： The invention provides a method of fabricating a capacitor with high capacitance. A substrate having word lines and bit lines is provided, and a dielectric layer is formed to cover the substrate. A contact window is formed in the dielectric layer to expose an active region. A conductive layer is formed to fill the contact window to connect with the active region. An insulating layer is formed on the conductive layer and the insulating layer and the conductive layer are defined. A hemispherical grained-Si (HSG-Si) layer is then formed on the substrate. An etching process is performed on the HSG-Si layer to expose the dielectric layer using a portion of the insulating layer as a mask. The insulating layer is removed. A storage node with a gear toothed profile is then formed.

摘要翻译： 本发明提供一种制造具有高电容的电容器的方法。 提供具有字线和位线的基板，并且形成介电层以覆盖基板。 在电介质层中形成接触窗口以暴露活性区域。 形成导电层以填充接触窗口以与有源区域连接。 在导电层上形成绝缘层，并且限定绝缘层和导电层。 然后在基板上形成半球形的Si（HSG-Si）层。 使用绝缘层的一部分作为掩模，在HSG-Si层上进行蚀刻处理以使介电层露出。 绝缘层被去除。 然后形成具有齿轮齿廓的存储节点。

公开(公告)号：US5585303A

公开(公告)日：1996-12-17

申请号：US608104

申请日：1996-02-28

申请人： Gary Hong ,  J. S. Jason Jenq

发明人： Gary Hong ,  J. S. Jason Jenq

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for manufacturing a DRAM capacitor on a substrate in which an insulator, a first barrier layer, a first conductive layer and a second barrier layer are sequentially applied over the gate electrode and source/drain areas of the substrate. Portions of the deposited layers above the source/drain areas are removed to form trenches which reach these areas. After portions of the second barrier layer and the first conductive layer are etched away, a conductive material layer is deposited thereover, an n-type dopant is doped into the conductive material layer, the dopant is diffused into the substrate to form n.sup.+ -type diffused regions, and the conductive material layer is shaped to form spaced-apart poly spacers and poly fins. Thereafter the first and the second barrier layers are removed to form a bottom plate of the DRAM capacitor which is defined by the first conductive layer, the poly spacers and the poly fins. Finally, a dielectric film is applied over the bottom plate and a further conductive layer is deposited thereover so that it forms a top plate of the DRAM capacitor. The resulting stack/trench capacitor has a larger dielectric film area and a correspondingly larger capacitance.

摘要翻译： 一种用于在衬底上制造DRAM电容器的方法，其中绝缘体，第一势垒层，第一导电层和第二阻挡层依次施加在衬底的栅极电极和源极/漏极区域上。 在源极/漏极区域上方的沉积层的部分被去除以形成到达这些区域的沟槽。 在第二阻挡层和第一导电层的部分被蚀刻掉之后，在其上沉积导电材料层，将n型掺杂剂掺杂到导电材料层中，掺杂剂扩散到衬底中以形成n +型扩散 区域，并且导电材料层被成形为形成间隔开的聚间隔物和多个翅片。 此后，去除第一和第二阻挡层以形成DRAM电容器的底板，其由第一导电层，多隔板和多个鳍片限定。 最后，将电介质膜施加在底板上，并在其上沉积另外的导电层，从而形成DRAM电容器的顶板。 所得到的堆叠/沟槽电容器具有较大的电介质膜面积和相应较大的电容。