公开(公告)号：US07326625B2

公开(公告)日：2008-02-05

申请号：US11052552

申请日：2005-02-07

Applicant: Joo-Hyun Jeong ,  Chul-Ho Chung

Inventor： Joo-Hyun Jeong ,  Chul-Ho Chung

IPC: H01L21/20

CPC classification number: H01L28/10 ,  H01L21/764 ,  H01L27/08

Abstract: In a method of forming a trench structure having a wide void therein, a first trench having a first width and a first depth is formed in a substrate. The first trench is filled with a first insulation layer pattern defining the void in the first trench. A second trench is formed on the first trench. The second trench has a second width wider than the first width and a second depth shallower than the first depth. The second trench is filled with a second insulation layer pattern. After an insulating interlayer on the substrate including the first and second trenches, a conductive line is formed on a portion of the insulating interlayer where the second trench is positioned so that an inductor is formed over the trench structure.

Abstract translation: 在形成其中具有宽空隙的沟槽结构的方法中，在衬底中形成具有第一宽度和第一深度的第一沟槽。 第一沟槽填充有限定第一沟槽中的空隙的第一绝缘层图案。 在第一沟槽上形成第二沟槽。 第二沟槽具有比第一宽度宽的第二宽度和比第一深度浅的第二深度。 第二沟槽填充有第二绝缘层图案。 在包括第一沟槽和第二沟槽的衬底上的绝缘中间层之后，在绝缘中间层的一部分上形成导电线，其中第二沟槽被定位，使得电感器形成在沟槽结构之上。

公开(公告)号：US08493709B2

公开(公告)日：2013-07-23

申请号：US13401233

申请日：2012-02-21

Applicant: Chul-Ho Chung

Inventor： Chul-Ho Chung

IPC: H01G4/30

CPC classification number: H01G4/228 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/43 ,  H01L2924/00

Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.

Abstract translation: 在电容器结构及其形成方法中，第一电极，第二电极和第一绝缘层依次形成在基板上。 第一和第二电极和第一绝缘层被衬底上的第二绝缘层覆盖。 第一插头通过第二绝缘层与第二电极接触。 第二插头通过第一和第二绝缘层与第一电极接触。 在第二绝缘层上形成第三绝缘层。 第三和第四梳状电极形成在第三绝缘层中。 第三电极与第一插头接触，第四电极与第二插头接触，同时面向第三电极。 因此，梳状电极的齿在第三绝缘层中交替排列并间隔开。

公开(公告)号：US08492822B2

公开(公告)日：2013-07-23

申请号：US12659446

申请日：2010-03-09

Applicant: Jin-Sung Lim ,  Chul-Ho Chung

Inventor： Jin-Sung Lim ,  Chul-Ho Chung

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L23/5222 ,  H01L21/76885 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing an LC circuit, including forming a first conductive layer pattern serving as a lower electrode of a capacitor on a first interlayer insulating layer, forming a dielectric layer pattern storing electric charges on the first conductive layer pattern, forming a second conductive layer pattern serving as an upper electrode of the capacitor on the dielectric layer pattern, forming a second interlayer insulating layer on the second conductive layer pattern, forming a contact via exposing one of the first or second conductive layer pattern in the second interlayer insulating layer, and filling the contact via with a contact plug, and forming a third conductive layer pattern on the second interlayer insulating layer having the contact plug, wherein the third conductive layer pattern is electrically connected to the contact plug, and is etched in a metal interconnection type layer and functions as an inductor.

Abstract translation: 一种用于制造LC电路的方法，包括在第一层间绝缘层上形成用作电容器的下电极的第一导电层图案，形成在第一导电层图案上存储电荷的介电层图案，形成第二导电层 形成在电介质层图案上的电容器的上电极，在第二导电层图案上形成第二层间绝缘层，通过暴露第二层间绝缘层中的第一或第二导电层图案之一形成接触;以及 通过接触塞填充接触孔，以及在具有接触插塞的第二层间绝缘层上形成第三导电层图案，其中第三导电层图案电连接到接触插塞，并且被蚀刻在金属互连型层 并用作电感器。

公开(公告)号：US20050176215A1

公开(公告)日：2005-08-11

申请号：US11052552

申请日：2005-02-07

Applicant: Joo-Hyun Jeong ,  Chul-Ho Chung

Inventor： Joo-Hyun Jeong ,  Chul-Ho Chung

IPC: H01L27/02 ,  H01L21/02 ,  H01L21/764 ,  H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L29/00

CPC classification number: H01L28/10 ,  H01L21/764 ,  H01L27/08

Abstract: In a method of forming a trench structure having a wide void therein, a first trench having a first width and a first depth is formed in a substrate. The first trench is filled with a first insulation layer pattern defining the void in the first trench. A second trench is formed on the first trench. The second trench has a second width wider than the first width and a second depth shallower than the first depth. The second trench is filled with a second insulation layer pattern. After an insulating interlayer on the substrate including the first and second trenches, a conductive line is formed on a portion of the insulating interlayer where the second trench is positioned so that an inductor is formed over the trench structure.

Abstract translation: 在形成其中具有宽空隙的沟槽结构的方法中，在衬底中形成具有第一宽度和第一深度的第一沟槽。 第一沟槽填充有限定第一沟槽中的空隙的第一绝缘层图案。 在第一沟槽上形成第二沟槽。 第二沟槽具有比第一宽度宽的第二宽度和比第一深度浅的第二深度。 第二沟槽填充有第二绝缘层图案。 在包括第一和第二沟槽的衬底上的绝缘中间层之后，在绝缘中间层的一部分上形成导电线，其中第二沟槽被定位，使得电感器形成在沟槽结构之上。

公开(公告)号：US09312184B2

公开(公告)日：2016-04-12

申请号：US14200274

申请日：2014-03-07

Applicant: Tea-Kwang Yu ,  Bae-Seong Kwon ,  Yong-Tae Kim ,  Chul-Ho Chung ,  Yong-Suk Choi

Inventor： Tea-Kwang Yu ,  Bae-Seong Kwon ,  Yong-Tae Kim ,  Chul-Ho Chung ,  Yong-Suk Choi

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L21/823462 ,  H01L21/823456 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate.

Abstract translation: 在制造半导体器件的方法中，在包括单元区域和逻辑区域的衬底的单元区域上形成分离栅极结构。 逻辑区域具有高电压区域，超高压区域和低电压区域，并且分离栅极结构包括第一栅极绝缘层图案，浮动栅极，隧道绝缘层图案和控制栅极。 在分离栅极结构和衬底上形成间隔层。 蚀刻间隔层以在分离栅极结构的侧壁上形成间隔物，并在衬底的超高电压区域上形成第二栅极绝缘层图案。 在基板的高电压区域，第二栅极绝缘层图案和基板的低电压区域中的每一个上形成栅电极。

公开(公告)号：US08198970B2

公开(公告)日：2012-06-12

申请号：US12453465

申请日：2009-05-12

Applicant: Tae-Hoon Choi ,  Chul-Ho Chung

Inventor： Tae-Hoon Choi ,  Chul-Ho Chung

IPC: H01F5/00 ,  H01F27/28

CPC classification number: H01F17/0013 ,  H03H7/1775 ,  H03H7/42

Abstract: A transformer of fully symmetric structure includes a primary coil assembly and a secondary coil assembly. The primary coil assembly includes a plurality of primary coils formed in a plurality of metal layers, and a first interlayer connection unit for connecting the primary coils. The secondary coil assembly includes a plurality of secondary coils formed in the plurality of metal layers, and a second interlayer connection unit for connecting the secondary coils. The primary and secondary coils formed in the same metal layer are concentric and axisymmetric with respect to a diameter line passing through a planar center point. A balanced-unbalanced transformer (balun) is a type of transformer that may be used to convert an unbalanced signal to a balanced one or vice versa. An integrated circuit may include a semiconductor substrate and a transformer. Electrical elements such as transistors may be formed on the semiconductor substrate.

Abstract translation: 完全对称结构的变压器包括初级线圈组件和次级线圈组件。 初级线圈组件包括形成在多个金属层中的多个初级线圈和用于连接初级线圈的第一层间连接单元。 次级线圈组件包括形成在多个金属层中的多个次级线圈和用于连接次级线圈的第二层间连接单元。 形成在同一金属层中的初级和次级线圈相对于通过平面中心点的直径线是同心的和轴对称的。 平衡 - 不平衡变压器（balun）是一种变压器，可用于将不平衡信号转换成平衡信号，反之亦然。 集成电路可以包括半导体衬底和变压器。 诸如晶体管的电气元件可以形成在半导体衬底上。

公开(公告)号：US08130483B2

公开(公告)日：2012-03-06

申请号：US12659687

申请日：2010-03-17

Applicant: Chul-Ho Chung

Inventor： Chul-Ho Chung

IPC: H01G4/30

CPC classification number: H01G4/228 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/43 ,  H01L2924/00

Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.

Abstract translation: 在电容器结构及其形成方法中，第一电极，第二电极和第一绝缘层依次形成在基板上。 第一和第二电极和第一绝缘层被衬底上的第二绝缘层覆盖。 第一插头通过第二绝缘层与第二电极接触。 第二插头通过第一和第二绝缘层与第一电极接触。 在第二绝缘层上形成第三绝缘层。 第三和第四梳状电极形成在第三绝缘层中。 第三电极与第一插头接触，第四电极与第二插头接触，同时面向第三电极。 因此，梳状电极的齿在第三绝缘层中交替排列并间隔开。

公开(公告)号：US20070216510A1

公开(公告)日：2007-09-20

申请号：US11804320

申请日：2007-05-17

Applicant: Joo-Hyun Jeong ,  Chul-Ho Chung

Inventor： Joo-Hyun Jeong ,  Chul-Ho Chung

IPC: H01F5/00

CPC classification number: H01F17/0006 ,  H01F27/34 ,  H01F41/041 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.

公开(公告)号：US07236081B2

公开(公告)日：2007-06-26

申请号：US11322753

申请日：2005-12-30

Applicant: Joo-Hyun Jeong ,  Chul-Ho Chung

Inventor： Joo-Hyun Jeong ,  Chul-Ho Chung

IPC: H01F5/00

CPC classification number: H01F17/0006 ,  H01F27/34 ,  H01F41/041 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.

Abstract translation: 在基板上形成电感图形。 在电感图案上形成具有凹凸结构的导电图案，以增加电感图案的表面积。 在电感器图案上形成绝缘层。 在形成凹槽之后，去除绝缘层以露出电感器图案，导电图案保形地形成在凹槽和绝缘层上。 因此，电感器图案的表面积以及电感器的厚度增加以获得高品质因数的电感器。

公开(公告)号：US20100238603A1

公开(公告)日：2010-09-23

申请号：US12659687

申请日：2010-03-17

Applicant: Chul-Ho Chung

Inventor： Chul-Ho Chung

IPC: H01G4/30

CPC classification number: H01G4/228 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/43 ,  H01L2924/00

Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.

Abstract translation: 在电容器结构及其形成方法中，第一电极，第二电极和第一绝缘层依次形成在基板上。 第一和第二电极和第一绝缘层被衬底上的第二绝缘层覆盖。 第一插头通过第二绝缘层与第二电极接触。 第二插头通过第一和第二绝缘层与第一电极接触。 在第二绝缘层上形成第三绝缘层。 第三和第四梳状电极形成在第三绝缘层中。 第三电极与第一插头接触，第四电极与第二插头接触，同时面向第三电极。 因此，梳状电极的齿在第三绝缘层中交替排列并间隔开。