公开(公告)号：US5465056A

公开(公告)日：1995-11-07

申请号：US333524

申请日：1994-11-02

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

IPC分类号： H03K19/177 ,  H03K19/173 ,  H03K19/0175

CPC分类号： H03K19/1736

摘要： A field programmable interconnect device (FPID) includes a set of ports and an array of switch cells for selectively interconnecting pairs of the ports. The switch cells are organized into a hierarchy of subarrays, and a control cell is provided for each subarray. Each switch cell includes a crosspoint switch and a single-bit memory. A bit stored in the memory indicates whether the switch, when enabled, is to interconnect its pair of FPID I/O ports. A data bit stored in each control cell indicates whether all switching cells of an associated subarray are enabled. In a "rapid connect" mode of operation, the FPID sets the state of the bit stored in any individual switch or control cell in response to parallel input data identifying the cell and indicating the state of the bit to be stored in the cell. In the rapid connect mode, the FPID can be programmed to rapidly switch connections between individual lines or between parallel buses connected to its ports.

摘要翻译： 现场可编程互连设备（FPID）包括一组端口和用于选择性地互连端口对的开关单元阵列。 开关单元被组织成子阵列的层次结构，并且为每个子阵列提供控制单元。 每个开关单元包括交叉点开关和单位存储器。 存储在存储器中的位表示交换机是否在使能时互连其对FPID I / O端口。 存储在每个控制单元中的数据位指示相关子阵列的所有开关单元是否被使能。 在“快速连接”操作模式中，FPID响应于识别单元的并行输入数据并指示要存储在单元中的位的状态来设置存储在任何单独的开关或控制单元中的位的状态。 在快速连接模式下，FPID可以被编程为快速切换各个线路之间或连接到其端口的并行总线之间的连接。

公开(公告)号：US5530814A

公开(公告)日：1996-06-25

申请号：US333290

申请日：1994-11-02

申请人： Chun C. D. Wong ,  Wen-Jai Hsieh ,  Chi-Song Horng

发明人： Chun C. D. Wong ,  Wen-Jai Hsieh ,  Chi-Song Horng

IPC分类号： G06F13/36 ,  G06F15/173 ,  H03K19/173 ,  H03K19/177 ,  H05K1/00 ,  G06F13/00

CPC分类号： G06F15/17375 ,  H03K19/1736 ,  H03K19/17704 ,  H05K1/0286

摘要： A hierarchical crossbar switch includes several switch arrays, each switch array including several switch cells. Each switch cell interconnects a unique pair of signal ports and provides a bi-directional signal path between the signal ports it interconnects when switched on by an enabling signal. A first memory array stores input data indicating particular switch cells to be switched on. A second memory array stores input data indicating particular ones of the switch arrays to be enabled. The crossbar switch also includes a logic cell array that reads the data stored in the first and second memories and sends separate control signals to each switch cell. Each control signal switches on the switch cell to which it is sent when data in the first and second memory arrays indicate both that the switch cell is to be switched on and that the switch cell array including the switch cell is to be enabled.

摘要翻译： 分层交叉开关包括几个开关阵列，每个开关阵列包括几个开关单元。 每个开关单元互连一个唯一的一对信号端口，并且在通过使能信号接通时在互连的信号端口之间提供双向信号路径。 第一存储器阵列存储指示要接通的特定开关单元的输入数据。 第二存储器阵列存储指示要启用的特定开关阵列的输入数据。 交叉开关还包括逻辑单元阵列，其读取存储在第一和第二存储器中的数据，并向每个开关单元发送单独的控制信号。 当第一和第二存储器阵列中的数据指示要切换开关单元并且包括开关单元的开关单元阵列将被启用时，每个控制信号切换其所发送的开关单元。

公开(公告)号：US5625780A

公开(公告)日：1997-04-29

申请号：US333484

申请日：1994-11-02

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

IPC分类号： G06F15/173 ,  H03K19/173 ,  H05K1/00 ,  G06F13/00 ,  G06F13/36

CPC分类号： H03K19/1736 ,  G06F15/17375 ,  H05K1/0286

摘要： A programmable backplane includes a motherboard having slots for receiving printed circuit boards (PCBs). A field programmable interconnect device (FPID) mounted on the motherboard includes a programmable crosspoint switch for selectively routing signals between terminals of the PCBs. The routing is determined by input programming data. The FPID bi-directionally buffers all signals passing between ports of the crosspoint switch and the PCB terminals and can alter signal routing dynamically in response to routing instructions generated by instruction sources mounted on or connected to the PCBs. The programmable backplane may be used as a communication hub in a communication network or parallel processing system.

摘要翻译： 可编程背板包括具有用于接收印刷电路板（PCB）的槽的主板。 安装在母板上的现场可编程互连设备（FPID）包括用于在PCB的端子之间选择性地路由信号的可编程交叉点开关。 路由由输入编程数据确定。 FPID双向缓冲在交叉点开关的端口和PCB端子之间通过的所有信号，并且可以响应于安装在或连接到PCB上的指令源生成的路由指令动态地改变信号路由。 可编程背板可以用作通信网络或并行处理系统中的通信集线器。

公开(公告)号：US5559971A

公开(公告)日：1996-09-24

申请号：US333371

申请日：1991-11-02

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

IPC分类号： G06F15/173 ,  H03K19/173 ,  H05K1/00 ,  G06F13/00 ,  H03K19/0175

CPC分类号： H03K19/1736 ,  G06F15/17375 ,  H05K1/0286

摘要： A hierarchical crosspoint array is formed by switch cells occupying separate rectangles in a common plane of an integrated circuit. The switch cells are arranged to form square subarrays which, along with a corresponding set of control cells form a compact square shaped crosspoint array. Each switch cell includes three I/O lines crossing in two orthogonal directions and mating with I/O lines of adjacent switch cells to form two orthogonal arrays of I/O lines. Pairs of orthogonal I/O lines are permanently interconnected where they intersect in switch cells along a main diagonal of the array to provide signal paths leading from separate ports along the edges of the array each extending the length and width of the crosspoint array. Each switch cell of a subarray selectively interconnects two such signal paths to provide a signal path between two ports in response to a combination of states of a bit stored in the switch cell and a bit stored in a control cell corresponding to the subarray. The control signal supplied to each subarray concurrently inhibits switch operation of all cells in the subarray. The crosspoint array can be made to quickly switch buses connected to its ports by changing only the relatively small amount of data stored in the control cells without having to change the relatively large amount of data stored in each switch cell.

摘要翻译： 分层交叉点阵列由在集成电路的公共平面中占据分离矩形的开关单元形成。 开关单元布置成形成方形子阵列，其与相应的一组控制单元一起形成紧凑的正方形交叉点阵列。 每个开关单元包括在两个正交方向上交叉的三个I / O线，并且与相邻开关单元的I / O线配合以形成两个I / O线的正交阵列。 正交I / O线对是永久互连的，它们沿着阵列的主对角线在开关单元中相交，以提供沿阵列边缘分离的端口的信号路径，每个端口延伸交叉点阵列的长度和宽度。 子阵列的每个开关单元响应于存储在开关单元中的位的状态的组合和存储在对应于子阵列的控制单元中的位组合而选择性地互连两个这样的信号路径以提供两个端口之间的信号路径。 提供给每个子阵列的控制信号同时禁止子阵列中所有单元的开关操作。 可以通过仅改变存储在控制单元中的较小量的数据来快速切换连接到其端口的总线，而不必改变存储在每个开关单元中的相对大量的数据。

公开(公告)号：US5616510A

公开(公告)日：1997-04-01

申请号：US472942

申请日：1995-06-06

申请人： Chun C. D. Wong

发明人： Chun C. D. Wong

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C27/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11556 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/3472 ,  G11C16/3481 ,  G11C27/005 ,  H01L27/115 ,  H01L29/7885 ,  G11C2211/5621 ,  G11C2211/5624 ,  G11C2211/5634

摘要： A highly compact nonvolatile solid state memory core is provided that stores and reproduces both digital and analog signals for multimedia applications. The memory core includes vertical electrically erasable and programmable read only memories (EEPROM) cells having, for example, a stacked gate or a split channel configuration. An array of EEPROM cells on the same chip is prewritten and is used as a reference for digital-analog conversions and for memory cell programming. An intelligent write method allows each memory cell to either store an analog signal or multiple digital signals. Based on the previously stored signal, the intelligent write method determines whether to charge or to discharge the floating gate associated with the selected memory cell. Thus, full erasure is not required prior to programming each memory cell. The present invention significantly increases the density of memory cell arrays while prolonging the useful life of the array.

摘要翻译： 提供了一种高度紧凑的非易失性固态存储器核，其存储并再现用于多媒体应用的数字和模拟信号。 存储器芯包括具有例如堆叠栅极或分离沟道配置的垂直电可擦除和可编程只读存储器（EEPROM）单元。 同一芯片上的EEPROM单元阵列被预写，并用作数模转换和存储单元编程的参考。 智能写入方法允许每个存储单元存储模拟信号或多个数字信号。 基于先前存储的信号，智能写入方法确定是否对与所选择的存储器单元相关联的浮动栅极进行充电或放电。 因此，在编程每个存储单元之前不需要完全擦除。 本发明显着提高了存储单元阵列的密度，同时延长了阵列的使用寿命。

公开(公告)号：US5386132A

公开(公告)日：1995-01-31

申请号：US970728

申请日：1992-11-02

申请人： Chun C. D. Wong

发明人： Chun C. D. Wong

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C27/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/06 ,  H01L29/68

CPC分类号： H01L27/11556 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/3472 ,  G11C16/3481 ,  G11C27/005 ,  H01L27/115 ,  H01L29/7885 ,  G11C2211/5621 ,  G11C2211/5624 ,  G11C2211/5634

摘要： A highly compact nonvolatile solid state memory core is provided that stores and reproduces both digital and analog signals for multimedia applications. The memory core includes vertical electrically erasable and programmable read only memories (EEPROM) cells having, for example, a stacked gate or a split channel configuration. An array of EEPROM cells on the same chip is prewritten and is used as a reference for digital-analog conversions and for memory cell programming. An intelligent write method allows each memory cell to either store an analog signal or multiple digital signals. Based on the previously stored signal, the intelligent write method determines whether to charge or to discharge the floating gate associated with the selected memory cell. Thus, full erasure is not required prior to programming each memory cell. The present invention significantly increases the density of memory cell arrays while prolonging the useful life of the array.

摘要翻译： 提供了一种高度紧凑的非易失性固态存储器核，其存储并再现用于多媒体应用的数字和模拟信号。 存储器芯包括具有例如堆叠栅极或分离沟道配置的垂直电可擦除和可编程只读存储器（EEPROM）单元。 同一芯片上的EEPROM单元阵列被预写，并用作数模转换和存储单元编程的参考。 智能写入方法允许每个存储单元存储模拟信号或多个数字信号。 基于先前存储的信号，智能写入方法确定是否对与所选择的存储器单元相关联的浮动栅极进行充电或放电。 因此，在编程每个存储单元之前不需要完全擦除。 本发明显着提高了存储单元阵列的密度，同时延长了阵列的使用寿命。