公开(公告)号：US5465056A

公开(公告)日：1995-11-07

申请号：US333524

申请日：1994-11-02

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

IPC分类号： H03K19/177 ,  H03K19/173 ,  H03K19/0175

CPC分类号： H03K19/1736

摘要： A field programmable interconnect device (FPID) includes a set of ports and an array of switch cells for selectively interconnecting pairs of the ports. The switch cells are organized into a hierarchy of subarrays, and a control cell is provided for each subarray. Each switch cell includes a crosspoint switch and a single-bit memory. A bit stored in the memory indicates whether the switch, when enabled, is to interconnect its pair of FPID I/O ports. A data bit stored in each control cell indicates whether all switching cells of an associated subarray are enabled. In a "rapid connect" mode of operation, the FPID sets the state of the bit stored in any individual switch or control cell in response to parallel input data identifying the cell and indicating the state of the bit to be stored in the cell. In the rapid connect mode, the FPID can be programmed to rapidly switch connections between individual lines or between parallel buses connected to its ports.

摘要翻译： 现场可编程互连设备（FPID）包括一组端口和用于选择性地互连端口对的开关单元阵列。 开关单元被组织成子阵列的层次结构，并且为每个子阵列提供控制单元。 每个开关单元包括交叉点开关和单位存储器。 存储在存储器中的位表示交换机是否在使能时互连其对FPID I / O端口。 存储在每个控制单元中的数据位指示相关子阵列的所有开关单元是否被使能。 在“快速连接”操作模式中，FPID响应于识别单元的并行输入数据并指示要存储在单元中的位的状态来设置存储在任何单独的开关或控制单元中的位的状态。 在快速连接模式下，FPID可以被编程为快速切换各个线路之间或连接到其端口的并行总线之间的连接。

公开(公告)号：US5530814A

公开(公告)日：1996-06-25

申请号：US333290

申请日：1994-11-02

申请人： Chun C. D. Wong ,  Wen-Jai Hsieh ,  Chi-Song Horng

发明人： Chun C. D. Wong ,  Wen-Jai Hsieh ,  Chi-Song Horng

IPC分类号： G06F13/36 ,  G06F15/173 ,  H03K19/173 ,  H03K19/177 ,  H05K1/00 ,  G06F13/00

CPC分类号： G06F15/17375 ,  H03K19/1736 ,  H03K19/17704 ,  H05K1/0286

摘要： A hierarchical crossbar switch includes several switch arrays, each switch array including several switch cells. Each switch cell interconnects a unique pair of signal ports and provides a bi-directional signal path between the signal ports it interconnects when switched on by an enabling signal. A first memory array stores input data indicating particular switch cells to be switched on. A second memory array stores input data indicating particular ones of the switch arrays to be enabled. The crossbar switch also includes a logic cell array that reads the data stored in the first and second memories and sends separate control signals to each switch cell. Each control signal switches on the switch cell to which it is sent when data in the first and second memory arrays indicate both that the switch cell is to be switched on and that the switch cell array including the switch cell is to be enabled.

摘要翻译： 分层交叉开关包括几个开关阵列，每个开关阵列包括几个开关单元。 每个开关单元互连一个唯一的一对信号端口，并且在通过使能信号接通时在互连的信号端口之间提供双向信号路径。 第一存储器阵列存储指示要接通的特定开关单元的输入数据。 第二存储器阵列存储指示要启用的特定开关阵列的输入数据。 交叉开关还包括逻辑单元阵列，其读取存储在第一和第二存储器中的数据，并向每个开关单元发送单独的控制信号。 当第一和第二存储器阵列中的数据指示要切换开关单元并且包括开关单元的开关单元阵列将被启用时，每个控制信号切换其所发送的开关单元。

公开(公告)号：US5625780A

公开(公告)日：1997-04-29

申请号：US333484

申请日：1994-11-02

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

IPC分类号： G06F15/173 ,  H03K19/173 ,  H05K1/00 ,  G06F13/00 ,  G06F13/36

CPC分类号： H03K19/1736 ,  G06F15/17375 ,  H05K1/0286

摘要： A programmable backplane includes a motherboard having slots for receiving printed circuit boards (PCBs). A field programmable interconnect device (FPID) mounted on the motherboard includes a programmable crosspoint switch for selectively routing signals between terminals of the PCBs. The routing is determined by input programming data. The FPID bi-directionally buffers all signals passing between ports of the crosspoint switch and the PCB terminals and can alter signal routing dynamically in response to routing instructions generated by instruction sources mounted on or connected to the PCBs. The programmable backplane may be used as a communication hub in a communication network or parallel processing system.

摘要翻译： 可编程背板包括具有用于接收印刷电路板（PCB）的槽的主板。 安装在母板上的现场可编程互连设备（FPID）包括用于在PCB的端子之间选择性地路由信号的可编程交叉点开关。 路由由输入编程数据确定。 FPID双向缓冲在交叉点开关的端口和PCB端子之间通过的所有信号，并且可以响应于安装在或连接到PCB上的指令源生成的路由指令动态地改变信号路由。 可编程背板可以用作通信网络或并行处理系统中的通信集线器。

公开(公告)号：US5559971A

公开(公告)日：1996-09-24

申请号：US333371

申请日：1991-11-02

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun C. D. Wong

IPC分类号： G06F15/173 ,  H03K19/173 ,  H05K1/00 ,  G06F13/00 ,  H03K19/0175

CPC分类号： H03K19/1736 ,  G06F15/17375 ,  H05K1/0286

摘要： A hierarchical crosspoint array is formed by switch cells occupying separate rectangles in a common plane of an integrated circuit. The switch cells are arranged to form square subarrays which, along with a corresponding set of control cells form a compact square shaped crosspoint array. Each switch cell includes three I/O lines crossing in two orthogonal directions and mating with I/O lines of adjacent switch cells to form two orthogonal arrays of I/O lines. Pairs of orthogonal I/O lines are permanently interconnected where they intersect in switch cells along a main diagonal of the array to provide signal paths leading from separate ports along the edges of the array each extending the length and width of the crosspoint array. Each switch cell of a subarray selectively interconnects two such signal paths to provide a signal path between two ports in response to a combination of states of a bit stored in the switch cell and a bit stored in a control cell corresponding to the subarray. The control signal supplied to each subarray concurrently inhibits switch operation of all cells in the subarray. The crosspoint array can be made to quickly switch buses connected to its ports by changing only the relatively small amount of data stored in the control cells without having to change the relatively large amount of data stored in each switch cell.

摘要翻译： 分层交叉点阵列由在集成电路的公共平面中占据分离矩形的开关单元形成。 开关单元布置成形成方形子阵列，其与相应的一组控制单元一起形成紧凑的正方形交叉点阵列。 每个开关单元包括在两个正交方向上交叉的三个I / O线，并且与相邻开关单元的I / O线配合以形成两个I / O线的正交阵列。 正交I / O线对是永久互连的，它们沿着阵列的主对角线在开关单元中相交，以提供沿阵列边缘分离的端口的信号路径，每个端口延伸交叉点阵列的长度和宽度。 子阵列的每个开关单元响应于存储在开关单元中的位的状态的组合和存储在对应于子阵列的控制单元中的位组合而选择性地互连两个这样的信号路径以提供两个端口之间的信号路径。 提供给每个子阵列的控制信号同时禁止子阵列中所有单元的开关操作。 可以通过仅改变存储在控制单元中的较小量的数据来快速切换连接到其端口的总线，而不必改变存储在每个开关单元中的相对大量的数据。

公开(公告)号：US5790048A

公开(公告)日：1998-08-04

申请号：US961545

申请日：1997-10-30

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

IPC分类号： H03K19/173 ,  H04Q1/00 ,  G06F13/00

CPC分类号： H03K19/1736

摘要： A crosspoint switch routes signals between its terminals in routing patterns defined by routing data from a host controller. The crosspoint switch includes an array of pass transistors. Each pass transistor, when turned on, provides a signal path interconnecting a separate, unique pair of the switch terminals. The crosspoint switch also includes two static random access memory banks. Each memory bank stores routing data defining a separate routing pattern and produces a separate set of output signals reflecting its stored data. A multiplexer delivers the output signals of a selected one of the memory banks to the switch array for controlling its pass transistors so that the switch array implements the routing pattern defined by the data in the selected memory bank. By loading routing data defining different routing patterns into the two memory banks, a host controller can thereafter quickly make the crosspoint switch alternate between the two routing patterns by toggling the multiplexer's control input.

摘要翻译： 交叉点交换机通过从主机控制器的路由数据定义的路由模式在其终端之间路由信号。 交叉点开关包括传输晶体管阵列。 每个通过晶体管在导通时提供一个信号路径，互连独立的一对开关端子。 交叉点开关还包括两个静态随机存取存储体。 每个存储体存储定义单独路由模式的路由数据，并产生反映其存储的数据的单独的一组输出信号。 多路复用器将所选择的一个存储器组的输出信号传送到开关阵列，以控制其传输晶体管，使得开关阵列实现由所选存储体中的数据定义的布线图案。 通过将定义不同路由模式的路由数据加载到两个存储体中，主控制器随后可以通过切换多路复用器的控制输入来快速地使交叉点开关交替在两个路由模式之间。

公开(公告)号：US5282271A

公开(公告)日：1994-01-25

申请号：US912975

申请日：1992-07-06

申请人： Wen-Jai Hsieh ,  Yih-Chyun Jeng ,  Chi-Song Horng ,  Keith Lofstrom

发明人： Wen-Jai Hsieh ,  Yih-Chyun Jeng ,  Chi-Song Horng ,  Keith Lofstrom

IPC分类号： G06F13/40 ,  H03K19/0175 ,  G06F13/00

CPC分类号： G06F13/4004 ,  H03K19/017581 ,  H03K19/01759

摘要： A field programmable interconnect device (FPID) flexibly interconnects a set of electronic components such as integrated circuits and other devices to one another. The FPID is an integrated circuit chip including a set of ports and a cross-point switch that can be programmed to logically connect any one port to any other port. Each FPID buffer port may be programmed to operate in various modes including unidirectional and bi-directional, with or without tristate control, and to operate at various input or output logic levels with adjustable pull up currents. Each FPID buffer port may also be programmed to perform various operations on buffered signals including adjustably delaying the signal, inverting it or forcing it high or low. The FPID is linked to a host computer via a bus that permits the host computer to program the FPID to make the desired connections, to select various modes of operation of buffers within the FPID and to read out data stored in the FPID. Each port of an FPID also samples and stores data indicating states of the signal passing through it over the last several system clock cycles. The FPID can subsequently read out the stored data to the host computer.

摘要翻译： 现场可编程互连设备（FPID）将诸如集成电路和其他设备的一组电子部件彼此灵活地互连。 FPID是一个集成电路芯片，包括一组端口和交叉点开关，可以将其编程为将任何一个端口逻辑连接到任何其他端口。 每个FPID缓冲器端口可以被编程为在具有或不具有三态控制的情况下以各种模式进行操作，包括单向和双向，并且可以在具有可调节上拉电流的各种输入或输出逻辑电平下工作。 每个FPID缓冲器端口也可以被编程为对缓冲信号执行各种操作，包括可调节地延迟信号，反相或强制其高或低。 FPID通过总线链接到主计算机，总线允许主计算机对FPID进行编程以进行所需的连接，以选择FPID内的缓冲器的各种操作模式并读出存储在FPID中的数据。 FPID的每个端口还采样和存储指示在最后几个系统时钟周期内通过它的信号的状态的数据。 FPID随后可以将存储的数据读出到主计算机。

公开(公告)号：US5428800A

公开(公告)日：1995-06-27

申请号：US960965

申请日：1992-10-13

申请人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng ,  Keith Lofstrom

发明人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng ,  Keith Lofstrom

IPC分类号： H03K19/173 ,  G06F13/40 ,  H03K19/0175 ,  H03K19/177 ,  G06F13/00 ,  H03K17/16

CPC分类号： G06F13/4004 ,  H03K19/017581 ,  H03K19/01759

摘要： A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up. The bi-directional buffer includes a register for storing and reading out data representing successive logic states of a signal on the first bus, thereby providing a history of data appearing on the bus.

摘要翻译： 双向缓冲器包括第一和第二单向缓冲器，连接用于在第一和第二总线之间以相反方向重新发送信号。 当外部总线驱动器将第一总线拉低时，第一单向缓冲器将第二总线拉低，并产生禁止第二单向缓冲器主动驱动第一总线的信号。 当外部总线驱动器允许第一总线返回到高逻辑电平时，第一单向缓冲器临时向第二总线提供高充电电流，以快速将其拉起。 类似地，当外部总线驱动器将第二总线拉低时，第二单向缓冲器将第一总线拉低，并产生禁止第一单向缓冲器主动驱动第二总线的信号。 当外部总线驱动器允许第二总线返回到高逻辑电平时，第二缓冲器暂时向第一总线提供高充电电流以快速将其拉起。 双向缓冲器包括用于存储和读出表示第一总线上的信号的连续逻辑状态的数据的寄存器，从而提供出现在总线上的数据历史。

公开(公告)号：US5710550A

公开(公告)日：1998-01-20

申请号：US516322

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe

IPC分类号： G06F15/173 ,  H04Q11/04 ,  H03K17/0412

CPC分类号： G06F15/17375 ,  H04Q11/0478

摘要： A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data. The FPID further includes a memory controller for receiving each command from the host controller and for writing data included in the command into each memory cell of a particular subset of the first and second memory cells upon receipt of the command. The address included in the command indicates the particular subset into which the controller is to write the data. The number of memory cells included in the particular subset is a variable function of the address.

摘要翻译： 现场可编程互连设备（FPID）响应于来自主机控制器的命令，有选择地在信号端口之间路由信号。 每个命令包括地址和数据。 FPID包括开关单元阵列，每个开关单元互连一个单独的端口对，并且每个具有第一和第二控制信号输入。 当第一和第二控制信号均被断言时，开关单元在其互连的一对端口之间提供信号路径。 FPID包括用于存储数据的第一和第二组存储器单元。 每个第一存储器单元对应于开关单元中的单独单元，并根据其存储的数据选择性地断言或解除输入到相应开关单元的第一控制信号。 每个第二存储器单元对应于单独的开关单元组，并根据其存储的数据选择性地断言或解除输入到相应组的每个开关单元的第二控制信号。 FPID还包括存储器控制器，用于从主机控制器接收每个命令，并且用于在接收到命令时将包括在命令中的数据写入第一和第二存储器单元的特定子集的每个存储单元。 命令中包含的地址表示控制器写入数据的特定子集。 包含在特定子集中的存储单元的数量是地址的可变函数。

公开(公告)号：US5428750A

公开(公告)日：1995-06-27

申请号：US171751

申请日：1993-12-21

申请人： Wen-Jai Hsieh ,  Chi-Song Horng

发明人： Wen-Jai Hsieh ,  Chi-Song Horng

IPC分类号： H03K19/173 ,  H05K1/00 ,  G06F13/00

CPC分类号： H03K19/1736 ,  H05K1/0286

摘要： A field programmable logic module provides a set of sockets for mounting electronic components, a set of connector pins for providing external access to the board, and a set of field programmable interconnect devices (FPIDs). The FPIDs are buffered, multiple port cross-point switches that may be programmed by a host computer to selectively connect terminals of the components mounted in the sockets to one another or to the external connector pins. Signal buffers within the FPID ports can be programmed to provide various types of buffering and logic operations on the signals routed by the FPIDs.

摘要翻译： 现场可编程逻辑模块提供一组插座，用于安装电子元件，一组连接器引脚，用于提供对板的外部访问，以及一组现场可编程互连设备（FPID）。 FPID是缓冲的，多端口交叉点开关，其可以由主机计算机来选择性地将安装在插座中的部件的端子彼此连接或连接到外部连接器引脚。 FPID端口中的信号缓冲器可以编程为对FPID路由的信号提供各种类型的缓冲和逻辑运算。

公开(公告)号：US5426738A

公开(公告)日：1995-06-20

申请号：US171752

申请日：1993-12-21

申请人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng

发明人： Wen-Jai Hsieh ,  Yih-Chyun Jenq ,  Chi-Song Horng

IPC分类号： H03K19/173 ,  H05K1/00 ,  G06F3/00

CPC分类号： H03K19/1736 ,  H05K1/0286

摘要： A field programmable circuit board provides a set of sockets for receiving electronic components, a set of connector pins for providing external access to the board and an array of field programmable interconnect devices (FPIDs). The FPIDs are buffered, multiple port cross-point switches that may be programmed by a host computer to selectively connect terminals of the components mounted in the sockets to one another or to the external connector pins. Signal buffers within the FPID ports automatically sense direction of flow of bidirectional signals routed by the FPIDs and buffer the signals in the appropriate direction. Each FPID buffer also samples and stores data indicating states of the buffered signals over several system clock cycles for subsequent read out by the host computer.

摘要翻译： 现场可编程电路板提供一组用于接收电子元件的插座，一组连接器引脚，用于提供对板的外部访问以及现场可编程互连器件（FPID）阵列。 FPID是缓冲的，多端口交叉点开关，其可以由主机计算机来选择性地将安装在插座中的部件的端子彼此连接或连接到外部连接器引脚。 FPID端口内的信号缓冲区会自动检测由FPID路由的双向信号的流向，并按适当的方向缓冲信号。 每个FPID缓冲器还在几个系统时钟周期上采样和存储指示缓冲信号状态的数据，以供主计算机随后读出。