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    RECONFIGURABLE ARITHMETIC UNIT AND HIGH-EFFICIENCY PROCESSOR HAVING THE SAME
    1.
    发明申请
    RECONFIGURABLE ARITHMETIC UNIT AND HIGH-EFFICIENCY PROCESSOR HAVING THE SAME 有权
    可重构算术单元和具有相同功能的高效处理器

    公开(公告)号：US20090150471A1

    公开(公告)日：2009-06-11

    申请号：US12136107

    申请日：2008-06-10

    申请人： Yil Suk YANG ,  Jung Hee SUK ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

    发明人： Yil Suk YANG ,  Jung Hee SUK ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

    IPC分类号： G06F17/10

    CPC分类号： G06F7/57 ,  G06F7/5324 ,  G06F7/5338

    摘要： Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.

    摘要翻译： 提供了一种可重构运算单元和具有该可重配置运算单元的处理器。 可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。 可重构算术单元包括用于编码乘数的展位编码器，用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数，用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积 产品，用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器（MUX），用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器（CPA），以输出运算结果。 算术单元可以根据指令作为加法器或乘法器进行操作，从而可以增加整个硬件的使用程度。

    LOW-POWER CLOCK GATING CIRCUIT
    2.
    发明申请
    LOW-POWER CLOCK GATING CIRCUIT 有权
    低功率时钟提升电路

    公开(公告)号：US20080129359A1

    公开(公告)日：2008-06-05

    申请号：US11945387

    申请日：2007-11-27

    申请人： Dae Woo LEE ,  Yil Suk YANG ,  Ik Jae CHUN ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

    发明人： Dae Woo LEE ,  Yil Suk YANG ,  Ik Jae CHUN ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

    IPC分类号： H03K3/356

    CPC分类号： H03K3/0375

    摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

    摘要翻译： 提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。 低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟 通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。 使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用 单阈值电压。

    PARALLEL PROCESSOR FOR EFFICIENT PROCESSING OF MOBILE MULTIMEDIA
    3.
    发明申请
    PARALLEL PROCESSOR FOR EFFICIENT PROCESSING OF MOBILE MULTIMEDIA 有权
    并行处理器对移动多媒体的高效处理

    公开(公告)号：US20080294875A1

    公开(公告)日：2008-11-27

    申请号：US12045844

    申请日：2008-03-11

    申请人： Chun Gi LYUH ,  Yil Suk YANG ,  Se Wan HEO ,  Soon Il YEO ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Se Hoon YOO

    发明人： Chun Gi LYUH ,  Yil Suk YANG ,  Se Wan HEO ,  Soon Il YEO ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Se Hoon YOO

    IPC分类号： G06F15/76 ,  G06F9/02

    CPC分类号： G06F15/8007

    摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

    摘要翻译： 提供了一种用于支持浮点运算的并行处理器。 并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。 为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。 使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。 此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

    ROW OF FLOATING POINT ACCUMULATORS COUPLED TO RESPECTIVE PES IN UPPERMOST ROW OF PE ARRAY FOR PERFORMING ADDITION OPERATION
    4.
    发明申请
    ROW OF FLOATING POINT ACCUMULATORS COUPLED TO RESPECTIVE PES IN UPPERMOST ROW OF PE ARRAY FOR PERFORMING ADDITION OPERATION 审中-公开
    浮动点累积器与适用于执行添加操作的PE阵列的更高层次的PES相关联的方法

    公开(公告)号：US20100257342A1

    公开(公告)日：2010-10-07

    申请号：US12817407

    申请日：2010-06-17

    申请人： Chun Gi LYUH ,  Yil Suk YANG ,  Se Wan HEO ,  Soon Il YEO ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Se Hoon YOO

    发明人： Chun Gi LYUH ,  Yil Suk YANG ,  Se Wan HEO ,  Soon Il YEO ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Se Hoon YOO

    IPC分类号： G06F9/302

    CPC分类号： G06F15/8007

    摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

    摘要翻译： 提供了一种用于支持浮点运算的并行处理器。 并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。 为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。 使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。 此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

    MULTIPLE-SIMD PROCESSOR FOR PROCESSING MULTIMEDIA DATA AND ARITHMETIC METHOD USING THE SAME
    5.
    发明申请
    MULTIPLE-SIMD PROCESSOR FOR PROCESSING MULTIMEDIA DATA AND ARITHMETIC METHOD USING THE SAME 审中-公开
    用于处理多媒体数据的多SIMD处理器和使用它的算术方法

    公开(公告)号：US20090144523A1

    公开(公告)日：2009-06-04

    申请号：US12174988

    申请日：2008-07-17

    申请人： Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

    发明人： Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

    IPC分类号： G06F15/80 ,  G06F9/02

    CPC分类号： G06F15/8007 ,  G06F9/30181 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

    摘要： A multiple-single instruction multiple data (SIMD) processor and an arithmetic method using the same are disclosed. When various arithmetic operations should be individually carried out by SIMD arithmetic units, control right is sub-divided to perform the arithmetic operations, such that the time of the arithmetic operations can be shortened and the efficiency thereof can be raised. When sub-divided control is not required, the control right is withdrawn and the arithmetic operations are carried out using a minimum number of program memories and a minimum number of SIMD arithmetic units, such that memory and power consumption thereof can be reduced.

    摘要翻译： 公开了一种多单指令多数据（SIMD）处理器及其运算方法。 当通过SIMD算术单元分别进行各种算术运算时，控制权被细分，进行算术运算，可以缩短算术运算的时间，提高效率。 当不需要分分割控制时，撤回控制权，并且使用最少数量的程序存储器和最小数量的SIMD运算单元执行算术运算，从而可以减少存储器和功耗。

    APPARATUS AND METHOD FOR CALCULATING SUM OF ABSOLUTE DIFFERENCES FOR MOTION ESTIMATION OF VARIABLE BLOCK
    6.
    发明申请
    APPARATUS AND METHOD FOR CALCULATING SUM OF ABSOLUTE DIFFERENCES FOR MOTION ESTIMATION OF VARIABLE BLOCK 有权
    用于计算可变块运动估计的绝对差异的装置和方法

    公开(公告)号：US20080292001A1

    公开(公告)日：2008-11-27

    申请号：US12105745

    申请日：2008-04-18

    申请人： Yil Suk YANG ,  Jung Hee SUK ,  Chun Gi LYUH ,  Ik Jae CHUN ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Jung Hoon KIM

    发明人： Yil Suk YANG ,  Jung Hee SUK ,  Chun Gi LYUH ,  Ik Jae CHUN ,  Tae Moon ROH ,  Jong Dae KIM ,  Ki Chul KIM ,  Jung Hoon KIM

    IPC分类号： H04N7/26

    CPC分类号： H04N19/00521 ,  H04N19/102 ,  H04N19/122 ,  H04N19/134 ,  H04N19/436 ,  H04N19/57 ,  H04N19/61 ,  H04N19/86

    摘要： Provided are an apparatus and method for calculating a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to a plurality of current frame macroblocks at a time. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in a plurality of serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.

    摘要翻译： 提供了一种用于计算能够相对于多个当前帧宏块同时并行计算SAD值的可变块的运动估计的绝对差（SAD）的装置和方法。 该装置包括PE阵列单元，该PE阵列单元包括以矩阵的形式排列的至少一个处理元件（PE），并且并行地计算设置在多个串行当前帧宏块中的至少一个像素的SAD值，本地存储器 包括当前帧宏块数据，参考帧宏块数据和参考帧搜索区域数据，以及将数据发送到在PE阵列单元中提供的每个PE，以及用于为在本地提供的数据进行命令的控制器 要发送对应于至少一个像素的存储器，其中PE阵列单元中提供的每个PE执行计算。

    BUS BRIDGE APPARATUS
    7.
    发明申请
    BUS BRIDGE APPARATUS 审中-公开

    公开(公告)号：US20130166801A1

    公开(公告)日：2013-06-27

    申请号：US13620294

    申请日：2012-09-14

    申请人： Ik Jae Jae CHUN ,  Chun-Gi LYUH ,  Jung Hee SUK ,  Sanghun YOON ,  Tae Moon ROH

    发明人： Ik Jae Jae CHUN ,  Chun-Gi LYUH ,  Jung Hee SUK ,  Sanghun YOON ,  Tae Moon ROH

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4059

    摘要： Disclosed is a bus bridge apparatus may prevent a transfer performance from being lowered due to bus protocol performance mismatch between interconnections. The bus bridge apparatus is used to transfer data to a slave device of a network-based interconnection from a master device of a bus-based interconnection, data of the master device may be buffered by an internal buffer, and may then be transferred to the slave device. At this time, lowering of a transfer efficiency may be prevented by converting a transfer timing of addresses and data to be optimized to a transfer protocol of the network-based interconnection through a protocol converter.

    摘要翻译： 公开了一种总线桥接装置可以防止由于互连之间的总线协议性能不匹配而导致传输性能降低。 总线桥装置用于从基于总线的互连的主设备将数据传送到基于网络的互连的从设备，主设备的数据可以由内部缓冲器缓冲，然后可以被传送到 从设备。 此时，可以通过协议转换器将要优化的地址和数据的传送定时转换为基于网络的互连的传输协议来防止传输效率的降低。

    IMAGE PROCESSING DEVICE
    8.
    发明申请
    IMAGE PROCESSING DEVICE 审中-公开
    图像处理装置

    公开(公告)号：US20100135396A1

    公开(公告)日：2010-06-03

    申请号：US12540722

    申请日：2009-08-13

    申请人： Jung Hee SUK ,  Chun-Gi LYUH ,  Tae Moon ROH ,  Jongdae KIM

    发明人： Jung Hee SUK ,  Chun-Gi LYUH ,  Tae Moon ROH ,  Jongdae KIM

    IPC分类号： H04N7/26

    CPC分类号： H04N19/436 ,  H04N19/109 ,  H04N19/147 ,  H04N19/176 ,  H04N19/61

    摘要： Provided is an image processing device. The image processing device includes: a plurality of operation units; and a controller unit storing an occurred bit amount to calculate a rate-distortion cost value and transmitting the occurred bit amount to each of the plurality of operation units, wherein at least one of the plurality of operation units calculates each distortion value with respect to a plurality of encoding modes and calculates each rate-distortion cost value with respect to the plurality of encoding modes using the calculated each distortion value and occurred bit amount.

    摘要翻译： 提供了一种图像处理装置。 图像处理装置包括：多个操作单元; 以及控制器单元，存储发生的比特量以计算速率失真成本值，并将所发生的比特量发送到多个操作单元中的每一个，其中多个操作单元中的至少一个针对一个操作单元计算每个失真值 多个编码模式，并且使用所计算的每个失真值和发生的位量来计算关于多个编码模式的每个速率 - 失真成本值。

    FEATURE VECTOR CLASSIFIER AND RECOGNITION DEVICE USING THE SAME
    9.
    发明申请
    FEATURE VECTOR CLASSIFIER AND RECOGNITION DEVICE USING THE SAME 审中-公开
    特征向量分类器和识别装置使用它

    公开(公告)号：US20130156319A1

    公开(公告)日：2013-06-20

    申请号：US13550833

    申请日：2012-07-17

    申请人： Chun-Gi LYUH ,  Ik Jae CHUN ,  Jung Hee SUK ,  Sanghun YOON ,  Tae Moon ROH

    发明人： Chun-Gi LYUH ,  Ik Jae CHUN ,  Jung Hee SUK ,  Sanghun YOON ,  Tae Moon ROH

    IPC分类号： G06K9/46

    CPC分类号： G06K9/6269

    摘要： Provided are a feature vector extractor and a recognition device using the same. The feature vector classifier includes a feature vector extractor configured to generate a feature vector and a normalized value from an input image and output the feature vector and the normalized value; and a feature vector classifier configured to normalize the feature vector based on the normalized value and classify the normalized feature vector to recognize the input image. Thus, during extraction and classification of a feature vector, time required for the extraction and classification and the size of hardware required are significantly reduced.

    摘要翻译： 提供了一种特征向量提取器和使用其的识别装置。 特征向量分类器包括：特征向量提取器，被配置为从输入图像生成特征向量和归一化值，并输出特征向量和归一化值; 以及特征矢量分类器，其被配置为基于归一化值对特征向量进行归一化，并且对归一化特征向量进行分类以识别输入图像。 因此，在特征向量的提取和分类期间，提取和分类所需的时间以及所需的硬件的大小显着降低。