公开(公告)号：US10385378B2

公开(公告)日：2019-08-20

申请号：US15655209

申请日：2017-07-20

Applicant: Chun-Cheng Kuo

Inventor： Chun-Cheng Kuo

IPC: C12Q1/02 ,  C12R1/89

Abstract: The present invention relates to a method for rapid detection of toxicity comprising the steps of: preparing a plant gel agar and a sample under study, mixing the agar gel with the sample under study to form a mixture, and measuring a coagulation time of the mixture to determine cytotoxicity of the sample under study.

公开(公告)号：US07872515B1

公开(公告)日：2011-01-18

申请号：US12606436

申请日：2009-10-27

Applicant: Chun-Cheng Kuo

Inventor： Chun-Cheng Kuo

IPC: H03H11/16

CPC classification number: H03K5/156 ,  H03K19/00361 ,  H03K2005/00052 ,  H03K2005/00286

Abstract: A phase interpolation device and a slew rate control device thereof. The slew rate control device comprises a slew rate control circuit, source followers and a comparator. The slew rate control circuit receives clock signals and a control signal, and adjusts slew rate of the clock signals according to the control signal. The source followers each comprise an input terminal and an output terminal. The input terminals of the source followers are coupled to the slew rate control circuit to receive the adjusted clock signals, respectively. The output terminals of the source followers are connected together at a node. The comparator has a first input terminal coupled to the node, a second input terminal receiving a voltage reference, and an output terminal providing the control signal for the slew rate control circuit. The setting of the voltage reference is dependent on the desired slew rate of the adjusted clock signals.

Abstract translation: 相位插值装置及其压摆率控制装置。 压摆率控制装置包括压摆率控制电路，源极跟随器和比较器。 转换速率控制电路接收时钟信号和控制信号，并根据控制信号调整时钟信号的转换速率。 源跟随器各自包括输入端子和输出端子。 源极跟随器的输入端子耦合到转换速率控制电路以分别接收经调整的时钟信号。 源跟随器的输出端在节点处连接在一起。 比较器具有耦合到节点的第一输入端子，接收电压基准的第二输入端子和为转换速率控制电路提供控制信号的输出端子。 参考电压的设置取决于调整后的时钟信号的所需转换速率。

公开(公告)号：US20110175652A1

公开(公告)日：2011-07-21

申请号：US12690752

申请日：2010-01-20

Applicant: Chun-Cheng Kuo

Inventor： Chun-Cheng Kuo

IPC: H03L7/087

CPC classification number: H03L7/1976 ,  H03L7/235

Abstract: A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference frequency and a divided signal from the frequency divider. The voltage-controlled oscillator generates the output frequency according to the phase difference. The frequency multiplier performs frequency multiplication on the output frequency to generate a multiplied signal, and the frequency multiplier comprises a second phase-locked loop, to form a second loop. The frequency divider performs frequency division on the multiplied signal to generate the divided signal. The divided signal and the reference frequency are compared by the phase detector to determine the phase difference.

Abstract translation: 分数N锁相环（PLL）包括相位检测器，压控振荡器（VCO），分频器和具有混合数乘法因子的倍频器。 相位检测器比较来自分频器的参考频率和分频信号之间的相位差。 压控振荡器根据相位差产生输出频率。 倍频器对输出频率执行倍频以产生相乘的信号，并且倍频器包括第二锁相环，以形成第二环路。 分频器对乘法信号进行分频，以产生分频信号。 分频信号和参考频率由相位检测器进行比较，以确定相位差。

公开(公告)号：US07734000B2

公开(公告)日：2010-06-08

申请号：US11118323

申请日：2005-05-02

Applicant: Chun-Cheng Kuo ,  Li-Ren Huang

Inventor： Chun-Cheng Kuo ,  Li-Ren Huang

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/107 ,  H04L7/033

Abstract: A clock and data recovery circuit comprising a phase detection circuit, first and second oscillators, and a flip-flop. The phase detection circuit outputs a detection signal according to a significant transition of an input signal. Each oscillator receives the detection signal and operates alternately in a clock and data recovery mode and a phase-locked mode. When the first oscillator operates in the clock and data recovery mode and outputs a first clock to control the flip-flop to output an output signal, the second oscillator operates in the phase-locked mode to adjust a frequency of a second clock. Before switching to the clock and data recovery mode, the second oscillator synchronizes the second clock with the first clock.

Abstract translation: 一种时钟和数据恢复电路，包括相位检测电路，第一和第二振荡器以及触发器。 相位检测电路根据输入信号的显着变化输出检测信号。 每个振荡器接收检测信号并在时钟和数据恢复模式和锁相模式下交替工作。 当第一振荡器在时钟和数据恢复模式下工作并且输出第一时钟以控制触发器输出输出信号时，第二振荡器在锁相模式下操作以调整第二时钟的频率。 在切换到时钟和数据恢复模式之前，第二个振荡器将第二个时钟与第一个时钟同步。

公开(公告)号：US20060140309A1

公开(公告)日：2006-06-29

申请号：US11118323

申请日：2005-05-02

Applicant: Chun-Cheng Kuo ,  Li-Ren Huang

Inventor： Chun-Cheng Kuo ,  Li-Ren Huang

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/107 ,  H04L7/033

Abstract: A clock and data recovery circuit comprising a phase detection circuit, first and second oscillators, and a flip-flop. The phase detection circuit outputs a detection signal according to a significant transition of an input signal. Each oscillator receives the detection signal and operates alternately in a clock and data recovery mode and a phase-locked mode. When the first oscillator operates in the clock and data recovery mode and outputs a first clock to control the flip-flop to output an output signal, the second oscillator operates in the phase-locked mode to adjust a frequency of a second clock. Before switching to the clock and data recovery mode, the second oscillator synchronizes the second clock with the first clock.

Abstract translation: 一种时钟和数据恢复电路，包括相位检测电路，第一和第二振荡器以及触发器。 相位检测电路根据输入信号的显着变化输出检测信号。 每个振荡器接收检测信号并在时钟和数据恢复模式和锁相模式下交替工作。 当第一振荡器在时钟和数据恢复模式下工作并且输出第一时钟以控制触发器输出输出信号时，第二振荡器在锁相模式下操作以调整第二时钟的频率。 在切换到时钟和数据恢复模式之前，第二个振荡器将第二个时钟与第一个时钟同步。

公开(公告)号：US08054114B2

公开(公告)日：2011-11-08

申请号：US12690752

申请日：2010-01-20

Applicant: Chun-Cheng Kuo

Inventor： Chun-Cheng Kuo

IPC: H03L7/06

CPC classification number: H03L7/1976 ,  H03L7/235

Abstract: A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference frequency and a divided signal from the frequency divider. The voltage-controlled oscillator generates the output frequency according to the phase difference. The frequency multiplier performs frequency multiplication on the output frequency to generate a multiplied signal, and the frequency multiplier comprises a second phase-locked loop, to form a second loop. The frequency divider performs frequency division on the multiplied signal to generate the divided signal. The divided signal and the reference frequency are compared by the phase detector to determine the phase difference.

Abstract translation: 分数N锁相环（PLL）包括相位检测器，压控振荡器（VCO），分频器和具有混合数乘法因子的倍频器。 相位检测器比较来自分频器的参考频率和分频信号之间的相位差。 压控振荡器根据相位差产生输出频率。 倍频器对输出频率执行倍频以产生相乘的信号，并且倍频器包括第二锁相环，以形成第二环路。 分频器对乘法信号进行分频，以产生分频信号。 分频信号和参考频率由相位检测器进行比较，以确定相位差。

公开(公告)号：US20070081619A1

公开(公告)日：2007-04-12

申请号：US11440001

申请日：2006-05-25

Applicant: Chun-Cheng Kuo ,  Tun-Shih Chen ,  Li-Ren Huang

Inventor： Chun-Cheng Kuo ,  Tun-Shih Chen ,  Li-Ren Huang

IPC: H04L7/00

CPC classification number: H04L7/0338 ,  H03L7/0805 ,  H03L7/24

Abstract: A clock generator including an edge detector, an oscillator, a frequency divider, and a selector. The edge detector generates a detection signal according to an edge of a data signal. The oscillator generates a first clock according to a control signal and controls the phase of the first clock according to the detection signal. The frequency divider processes the first clock to generate a second clock and is reset by the detection signal. The selector selectively outputs the first clock or the second clock according to an external signal.

Abstract translation: 一种时钟发生器，包括边缘检测器，振荡器，分频器和选择器。 边缘检测器根据数据信号的边沿产生检测信号。 振荡器根据控制信号产生第一时钟，并根据检测信号控制第一时钟的相位。 分频器处理第一时钟以产生第二时钟并由检测信号复位。 选择器根据外部信号选择性地输出第一时钟或第二时钟。