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1.发明授权公开(公告)号：US11218155B2
公开(公告)日：2022-01-04
申请号：US17101665
申请日：2020-11-23
申请人： Ciena Corporation
发明人： Tingjun Wen , Sadok Aouini , Naim Ben-Hamida , Mahdi Parvizi , Matthew Mikkelsen
摘要： Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.
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公开(公告)号：US20240030932A1
公开(公告)日：2024-01-25
申请号：US17869173
申请日：2022-07-20
申请人： Ciena Corporation
发明人： Tingjun Wen , Sadok Aouini , Naim Ben-Hamida , Matthew Mikkelsen , Soheyl Ziabakhsh Shalmani , Mohammad Honarparvar
IPC分类号： H03M3/00
摘要： Described herein is a fractional phase locked loop with sigma-delta modulator (SDM) quantization noise cancellation. The fractional phase includes a digital filter configured to receive an error signal based on a comparison of a reference clock and a feedback clock, a controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on a control signal output by the digital filter, the feedback clock being based on the output clock, a sigma-delta modulator configured to control division of the output clock to generate a divided output clock which includes a sigma-delta modulator quantization noise and a digital-to-time converter configured to receive a cancellation code from an integrator in the sigma-delta modulator and cancel the sigma-delta modulator quantization noise in the divided output clock with the cancellation code to generate the feedback clock.
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公开(公告)号：US11804847B2
公开(公告)日：2023-10-31
申请号：US16205308
申请日：2018-11-30
申请人： Ciena Corporation
发明人： Sadok Aouini , Matthew Mikkelsen , Naim Ben-Hamida , Mahdi Parvizi , Tingjun Wen , Calvin Plett
IPC分类号： H03L7/197
CPC分类号： H03L7/1976
摘要： A circuit includes a programmable frequency divider which receives a high-speed clock, fin, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.
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公开(公告)号：US10979059B1
公开(公告)日：2021-04-13
申请号：US17079805
申请日：2020-10-26
申请人： Ciena Corporation
发明人： Soheyl Ziabakhsh Shalmani , Sadok Aouini , Matthew Mikkelsen , Hazem Beshara , Tingjun Wen , Mohammad Honarparvar , Naim Ben-Hamida
摘要： Described herein are apparatus and methods for a successive approximation register (SAR) analog-to-digital (ADC) based phase-locked loop (PLL) with programmable range. A multi-bit digital phase locked loop includes a multi-bit phase frequency detector configured to output a multi-bit error signal based on a reference clock, a feedback clock sampled using the reference clock, and a threshold voltage, a multi-bit digital low pass filter configured to apply a variable gain to the multi-bit error signal, a current steered digital-to-analog converter configured to generate a control current based on a gain applied multi-bit error signal and multi-bit digital phase locked loop control parameters, a controlled oscillator configured to adjust a frequency of the controlled oscillator based on the control current to generate an output clock, the feedback clock being based on the output clock, and a programmable edge time controller configured to adjust a slope of an edge of the feedback clock.
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5.发明申请公开(公告)号：US20210273644A1
公开(公告)日：2021-09-02
申请号：US17101665
申请日：2020-11-23
申请人： Ciena Corporation
发明人： Tingjun Wen , Sadok Aouini , Naim Ben-Hamida , Mahdi Parvizi , Matthew Mikkelsen
摘要： Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.
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6.发明申请公开(公告)号：US20200177194A1
公开(公告)日：2020-06-04
申请号：US16205308
申请日：2018-11-30
申请人： Ciena Corporation
发明人： Sadok Aouini , Matthew Mikkelsen , Naim Ben-Hamida , Mahdi Parvizi , Tingjun Wen , Calvin Plett
IPC分类号： H03L7/197
摘要： A circuit includes a programmable frequency divider which receives a high-speed clock, fin, as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.
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公开(公告)号：US20240313801A1
公开(公告)日：2024-09-19
申请号：US18673969
申请日：2024-05-24
申请人： Ciena Corporation
发明人： Tingjun Wen , Sadok Aouini , Naim Ben-Hamida , Matthew Mikkelsen , Soheyl Ziabakhsh Shalmani , Mohammad Honarparvar
IPC分类号： H03M3/00
摘要： Described herein is a fractional phase locked loop with sigma-delta modulator (SDM) quantization noise cancellation. The fractional phase includes a digital filter configured to receive an error signal based on a comparison of a reference clock and a feedback clock, a controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on a control signal output by the digital filter, the feedback clock being based on the output clock, a sigma-delta modulator configured to control division of the output clock to generate a divided output clock which includes a sigma-delta modulator quantization noise and a digital-to-time converter configured to receive a cancellation code from an integrator in the sigma-delta modulator and cancel the sigma-delta modulator quantization noise in the divided output clock with the cancellation code to generate the feedback clock.
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公开(公告)号：US12034460B2
公开(公告)日：2024-07-09
申请号：US17869173
申请日：2022-07-20
申请人： Ciena Corporation
发明人： Tingjun Wen , Sadok Aouini , Naim Ben-Hamida , Matthew Mikkelsen , Soheyl Ziabakhsh Shalmani , Mohammad Honarparvar
IPC分类号： H03M3/00
摘要： Described herein is a fractional phase locked loop with sigma-delta modulator (SDM) quantization noise cancellation. The fractional phase includes a digital filter configured to receive an error signal based on a comparison of a reference clock and a feedback clock, a controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on a control signal output by the digital filter, the feedback clock being based on the output clock, a sigma-delta modulator configured to control division of the output clock to generate a divided output clock which includes a sigma-delta modulator quantization noise and a digital-to-time converter configured to receive a cancellation code from an integrator in the sigma-delta modulator and cancel the sigma-delta modulator quantization noise in the divided output clock with the cancellation code to generate the feedback clock.
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