公开(公告)号：US10433054B1

公开(公告)日：2019-10-01

申请号：US15939994

申请日：2018-03-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Ian Johnson Smith ,  James Thomas Deas ,  Vivek Saraf

IPC: H03G11/00 ,  H04R3/00 ,  H04R19/04 ,  H04R29/00

Abstract: The present disclosure relates to a protection system for protecting a MEMS transducer of a MEMS device from electrostatic capture, wherein the MEMS transducer is operable in a normal-sensitivity, mode and in a reduced-sensitivity mode. The protection system comprises: an overload detector for detecting an overload condition arising as a result of an excessive sound pressure level at the MEMS transducer; a signal estimator configured to generate an estimate of a sound pressure level at the MEMS transducer; and a controller configured, in response to detection by the overload detector of an overload condition, to: disable an output of the MEMS transducer; and after a delay of a first predetermined period of time: cause the MEMS transducer to operate in the reduced-sensitivity mode; enable the output of the MEMS transducer; and cause the MEMS transducer to return to the normal-sensitivity mode if the estimate of the sound pressure level generated by the signal estimator while the MEMS transducer is operating in the reduced-sensitivity mode is below a safe sound pressure level threshold for a second predetermined period of time.

公开(公告)号：US20180324525A1

公开(公告)日：2018-11-08

申请号：US15586023

申请日：2017-05-03

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Vivek Saraf ,  Axel Thomsen ,  Ravi Kummaraguntla ,  John C. Tucker

IPC: H04R3/04 ,  H03H7/40

CPC classification number: H04R3/04 ,  H03F3/185 ,  H03F2200/03 ,  H03F2200/18 ,  H03H7/40 ,  H04R3/00 ,  H04R2201/003

Abstract: Input impedance biasing may be improved with an ultra-high-input-impedance biasing circuit having low temperature variation. The impedance biasing circuit may include a first transistor coupled to a first power supply and a second transistor coupled to a second power supply. A gate of the first transistor may be coupled to a gate of the second transistor at an intermediate bias node. The first transistor and the second transistor may provide a selected DC impedance at the intermediate bias node. The impedance may be used to provide low-pass and or high-pass filtering of audio signals and/or noise.

公开(公告)号：US10123117B1

公开(公告)日：2018-11-06

申请号：US15586023

申请日：2017-05-03

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Vivek Saraf ,  Axel Thomsen ,  Ravi Kummaraguntla ,  John C. Tucker

IPC: H04R3/00 ,  H04R3/04 ,  H03H7/40

CPC classification number: H04R3/04 ,  H03F3/185 ,  H03F2200/03 ,  H03F2200/18 ,  H03H7/40 ,  H04R3/00 ,  H04R2201/003

Abstract: Input impedance biasing may be improved with an ultra-high-input-impedance biasing circuit having low temperature variation. The impedance biasing circuit may include a first transistor coupled to a first power supply and a second transistor coupled to a second power supply. A gate of the first transistor may be coupled to a gate of the second transistor at an intermediate bias node. The first transistor and the second transistor may provide a selected DC impedance at the intermediate bias node. The impedance may be used to provide low-pass and or high-pass filtering of audio signals and/or noise.