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公开(公告)号：US4249253A
公开(公告)日：1981-02-03
申请号：US973448
申请日：1978-12-26
CPC分类号： G06F11/1052
摘要： A memory system wherein data is stored along with a SEC-DED error detecting and correcting code. Means are provided for selecting either a direct readout path for data from the memory when no readout errors have been detected for the memory address being accessed, or an alternate readout path including circuits for checking and correcting errors when an error condition has been detected. An auxiliary memory is provided for storing error flag bits indicating memory zones which have produced erroneous readouts, whereby the system is controlled such that high speed direct read cycles are executed for no-error memory zones and optimum memory accessing time is achieved without sacrificing the reliability achieved through use of the error correcting codes.
摘要翻译： 存储系统，其中数据与SEC-DED错误检测和校正码一起存储。 提供了用于当没有检测到正被访问的存储器地址的读出错误时选择来自存储器的数据的直接读出路径的装置，或者包括用于当检测到错误状况时检查和校正错误的电路的备选读出路径。 提供了一个辅助存储器，用于存储指示已经产生错误读出的存储器区域的错误标志位，由此系统被控制，使得对无错误存储器区域执行高速直接读取周期，并且在不牺牲可靠性的情况下实现最佳存储器访问时间 通过使用纠错码实现。
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公开(公告)号：US3972033A
公开(公告)日：1976-07-27
申请号：US535751
申请日：1974-12-23
申请人： Ezio Cislaghi , Claudio Gentili , Ermanno Maccario
发明人： Ezio Cislaghi , Claudio Gentili , Ermanno Maccario
CPC分类号： G06F11/1016 , G06F11/1032
摘要： A semiconductor memory includes means for separating the causes of error affecting the addressing and recording of information bits from those affecting check, or parity, bits. The recording words comprise 16 information bits, and are divided into two "bytes", of eight bits each. Each byte is provided with its own check bit; and two half-words of nine bits are recorded at the same address. Each submodule of the memory comprises two printed-circuit cards. The first card supports the integrated memory units wherein, for each word, the information bits of the first byte and the check bit of the second byte are recorded; the second card supports the memory units wherein the information bits of the second byte and the check bit of the first byte are recorded. Since an error cause affecting the control or the addressing circuits mounted on a card does not affect the recording and the addressing circuits of the second card, the recording or addressing of the information bits on one card will differ from the recording and addressing of the related check bit on the other card. Both bytes may be written or read out separately; and the writing or the reading-out signals of the information bits are independent from the writing or reading-out signal of the related check bits for both cards.
摘要翻译： 半导体存储器包括用于分离影响信息位的寻址和记录的原因与影响检查或奇偶校验的那些的原因的装置。 记录字包括16个信息位，并被分成两个“字节”，每个字节为8位。 每个字节都有自己的检查位; 并且在相同的地址记录了两个九位的半字。 存储器的每个子模块包括两个印刷电路卡。 第一卡支持集成存储器单元，其中对于每个字，记录第一字节的信息位和第二字节的校验位; 第二卡支持其中记录第二字节的信息位和第一字节的校验位的存储单元。 由于影响安装在卡上的控制或寻址电路的错误不会影响第二张卡的记录和寻址电路，所以一张卡上的信息位的记录或寻址将不同于相关的记录和寻址 检查另一张卡上的位。 两个字节可以单独写入或读出; 并且信息位的写入或读出信号独立于两个卡的相关校验位的写入或读出信号。
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公开(公告)号：US4133051A
公开(公告)日：1979-01-02
申请号：US535267
申请日：1974-12-23
申请人： Claudio Gentili
发明人： Claudio Gentili
IPC分类号： G11C11/404 , G11C11/405 , G11C11/406 , G11C13/00 , G11C11/40
CPC分类号： G11C11/406 , G11C11/404 , G11C11/405
摘要： A semiconductor memory is provided with means for refreshing the memory. Interrupt requests generated by the memory initiate refreshing cycles which are uniformly distributed during periods of normal operation of the memory, each cycle for a row of the memory. In a first time interval, an interrupt request has a low priority level and does not necessarily interrupt the operation of the computer. If the low priority interrupt request is not responded to, a second interrupt request with a high priority level is generated; this high priority level second interrupt request is responded to without fail.
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