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公开(公告)号：US4249253A
公开(公告)日：1981-02-03
申请号：US973448
申请日：1978-12-26
CPC分类号： G06F11/1052
摘要： A memory system wherein data is stored along with a SEC-DED error detecting and correcting code. Means are provided for selecting either a direct readout path for data from the memory when no readout errors have been detected for the memory address being accessed, or an alternate readout path including circuits for checking and correcting errors when an error condition has been detected. An auxiliary memory is provided for storing error flag bits indicating memory zones which have produced erroneous readouts, whereby the system is controlled such that high speed direct read cycles are executed for no-error memory zones and optimum memory accessing time is achieved without sacrificing the reliability achieved through use of the error correcting codes.
摘要翻译： 存储系统，其中数据与SEC-DED错误检测和校正码一起存储。 提供了用于当没有检测到正被访问的存储器地址的读出错误时选择来自存储器的数据的直接读出路径的装置，或者包括用于当检测到错误状况时检查和校正错误的电路的备选读出路径。 提供了一个辅助存储器，用于存储指示已经产生错误读出的存储器区域的错误标志位，由此系统被控制，使得对无错误存储器区域执行高速直接读取周期，并且在不牺牲可靠性的情况下实现最佳存储器访问时间 通过使用纠错码实现。
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2.发明授权Data processing system having dual arbiter for controlling access to a system bus 失效具有用于控制对系统总线的访问的双仲裁器的数据处理系统
公开(公告)号：US5038276A
公开(公告)日：1991-08-06
申请号：US494659
申请日：1990-03-16
IPC分类号： G06F13/364
CPC分类号： G06F13/364
摘要： A data processing system having a dual arbiter for controlling access to a system bus where two processors, each clocked by one of two timing signals having equal periods but out of phase by half a period, operate synchronously each to the other, but outphased by the half period of the clock signal, and generate equal priority signals requesting access to a system bus, each processor in a time distinct and non overlapped phase of the respective timing signals, and where an arbitration unit grants system bus access to either one or the other requesting processor on the time order in which the access requesting signals are received, the granting being performed asynchronously and without sampling and set up delays.
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3.发明授权Multiprocessor system with global data replication and two levels of address translation units 失效具有全球数据复制和地址转换单位两级的多处理器系统
公开(公告)号：US5247629A
公开(公告)日：1993-09-21
申请号：US469870
申请日：1990-01-24
CPC分类号： G06F12/0284 , G06F12/0692 , G06F12/1027
摘要： In a multiprocessor system having global data replication in each of the local memories, each associated with one of the processors, the global data allocation in the several local memories is performed by translating global data logical addresses into addresses conventionally defined as real, the translation being performed by a first translation unit associated with and managed by the processor which generates the global data. The first translation is followed by the translation of the real address into a physical address generally differing for each local memory and performed by a plurality of translation units, each associated with one of the local memories and managed by the processor associated with that local memory.
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4.发明授权Memory module selection and reconfiguration apparatus in a data processing system 失效数据处理系统中的存储器模块选择和重新配置装置
公开(公告)号：US4571676A
公开(公告)日：1986-02-18
申请号：US422772
申请日：1982-09-24
CPC分类号： G06F12/0653
摘要： A memory module selection and reconfiguration apparatus in a data processing system wherein a modular working memory formed by a plurality of memory modules sends to a central processing unit information related to the capacities of the constituting modules (M1, M2, M3, M4) during the system initialization. The central unit processes such information and provides memory, via a channel (30), with information representative of the capacity of the first modules (G1), of the sum of the capacities of the first and second module (G2), of the sum of the capacities of the first, second and third module (G3) and so on, up to the total capacity of the working memory. This information is stored into registers (31, 32), each one related to a possible module, of a module selection unit included inside the working memory. When the memory is addressed, the most significant address portion (BA 03-06) is compared simultaneously by several comparators (33, 34, 35, 36), one for each register, with the content of the several registers. The result of the comparison from the comparators are applied to a decoder (37) which generates signals selecting one among the several memory modules.
摘要翻译： 一种数据处理系统中的存储器模块选择和重新配置装置，其中由多个存储器模块形成的模块化工作存储器在中间处理单元期间将与构成模块（M1，M2，M3，M4）的容量有关的信息发送到中央处理单元 系统初始化。 中央单元处理这样的信息，并且经由信道（30）向存储器提供表示第一和第二模块（G2）的容量之和的第一模块（G1）的容量的信息，总和 的第一，第二和第三模块（G3）的容量等等，直到工作记忆体的总容量。 该信息被存储在包括在工作存储器内部的模块选择单元的与可能的模块相关的寄存器（31,32）中。 当存储器被寻址时，最高有效地址部分（BA 03-06）被几个比较器（33,34,35,36）同时比较，每个寄存器一个与几个寄存器的内容相比较。 比较器的比较结果被应用于产生选择多个存储器模块之一的信号的解码器（37）。
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公开(公告)号：US4592011A
公开(公告)日：1986-05-27
申请号：US547268
申请日：1983-10-31
CPC分类号： G06F12/0684 , G06F12/0653
摘要： In a data processing system wherein a memory is comprised of an unknown plurality of memory blocks of a basic capacity, arranged in an unknown plurality of modules which have an unknown capacity multiple of the basic capacity, a method addresses the memory location which involves the selection of the module containing such locations by use of a directory having a plurality of addressable locations. The initial loading of the directory with codes corresponding to the real constituent of the memory is performed by writing into the directory locations a binary code assigning the related memory blocks to a hypothetical first module, writing test codes into memory locations each belonging to a different block, reading out the contents of the same memory locations and comparing such contents with the test codes to determine if a first module is present and if such memory locations and the pertaining blocks belong to the first module, writing into the directory locations whose related memory block do not belong to the first module a binary code assigning the related memory blocks to a hypothetical second module, writing test codes into memory locations each belonging to a different block assigned to the second module, reading out the contents of the same memory locations and comparing such contents with the test codes to determine if a second module is present and if such memory locations and related memory blocks belong to the second module, and repeating the above operations for further subsequent modules.
摘要翻译： 在一种数据处理系统中，其中存储器由未知的具有基本容量的多个存储块组成，其布置在具有未知容量倍数的基本容量的未知多个模块中，一种寻址涉及选择的存储器位置的方法 通过使用具有多个可寻址位置的目录来包含这些位置的模块。 通过向目录位置写入将相关存储块分配给假想的第一模块的二进制代码，将测试代码写入每个属于不同块的存储器位置来执行具有与存储器的实际组成部分对应的代码的目录的初始加载 读出相同存储器位置的内容，并将这些内容与测试代码进行比较以确定第一模块是否存在，并且如果这样的存储器位置和相关块属于第一模块，则写入相关存储块 不属于第一模块，将相关存储器块分配给假想的第二模块的二进制代码，将测试代码写入每个属于分配给第二模块的不同块的存储器位置，读出相同存储器位置的内容并比较 这些内容带有测试代码，以确定是否存在第二个模块，并且是否存在这样的存储器位置 ns和相关的存储器块属于第二个模块，并对后续的后续模块重复上述操作。
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公开(公告)号：US4517681A
公开(公告)日：1985-05-14
申请号：US474915
申请日：1983-03-14
CPC分类号： H03K5/1502 , G06F1/04 , H03K5/15066 , H03K5/15093
摘要： A digital timing unit for timing a data processing system or units thereof, wherein the output signals of a shift register are applied to a plurality of EXCLUSIVE OR gates (G.sub.1) . . . (G.sub.n). The shift register is activated from a known state so that an electric transition signal is shifted through the register cells. A timing cycle is thus defined which is utilized to set the register in a second known state. Feedback and control logic are provided for activating the register independently of its state and keeping it in the state occurring at the end of a timing cycle until a new start signal is received. Shifting of the register is caused by timing pulses generated by an oscillator (1). The timing signals generated by the timing unit and present on the output terminals of the EXCLUSIVE OR may be modified, as to the length, by changing the oscillator period and/or the connection between the EXCLUSIVE OR inputs and the outputs of the shift register.
摘要翻译： 一种数字定时单元，用于定时数据处理系统或其单元，其中移位寄存器的输出信号被施加到多个独占或门（G1）。 。 。 （Gn）。 从已知状态激活移位寄存器，使得电转移信号通过寄存器单元移位。 因此定义了用于将寄存器设置在第二已知状态的定时周期。 提供反馈和控制逻辑，用于独立于其状态激活寄存器，并将其保持在定时周期结束时发生的状态，直到接收到新的起始信号。 寄存器的移位是由振荡器（1）产生的定时脉冲引起的。 通过改变振荡器周期和/或EXCLUSIVE OR输入与移位寄存器的输出之间的连接，可以修改由定时单元产生并存在于EXCLUSIVE OR的输出端上的定时信号。
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