摘要:
A cochlear implant system has an implantable portion that includes a stimulator module for producing for the auditory system of a user an electrical stimulation signal representative of an acoustic signal. The implantable portion further includes a battery for supplying power to the stimulator module, a receiver module for receiving an electrical power signal across the skin of a user, and a recharge module that uses the electrical power signal to recharge the battery. The recharge module recharges the battery at less than the maximum recharge rate.
摘要:
A cochlear implant system has a signal processor that fits in the ear canal of a user. The signal processor processes an acoustic signal present in the ear of the user to produce a representative radio signal. A power transmitter transmits an electrical power signal through the skin of the user. A cochlear implant receives the radio signal and the electrical power signal and produces for the auditory nerve of the user an electrical stimulation signal representative of the acoustic signal.
摘要:
A cochlear implant system has an implantable portion that includes a stimulator module for producing for the auditory system of a user an electrical stimulation signal representative of an acoustic signal. The implantable portion further includes a battery for supplying power to the stimulator module, a receiver module for receiving an electrical power signal across the skin of a user, and a recharge module that uses the electrical power signal to recharge the battery. The recharge module recharges the battery at less than the maximum recharge rate.
摘要:
A cochlear implant system has an implantable portion that includes a stimulator module for producing for the auditory system of a user an electrical stimulation signal representative of an acoustic signal. The implantable portion further includes a battery for supplying power to the stimulator module, a receiver module for receiving an electrical power signal across the skin of a user, and a recharge module that uses the electrical power signal to recharge the battery. The recharge module recharges the battery at less than the maximum recharge rate.
摘要:
A method of activating at least two electrodes in a multichannel electrode array using channel specific sampling sequences is presented. A channel specific sampling sequence is defined for each electrode, the sequence having a particular duration, pulse amplitude distribution, and number of pulses. A weighting factor is applied to the channel specific sampling sequence. Each electrode in the multichannel electrode array is then simultaneously activated using sign-correlated pulses, the sign-correlated pulses based on parameters of spatial channel interaction reflecting geometric overlapping of electrical fields from each electrode, non-linear compression, and each electrode's weighted channel specific sampling sequence.
摘要:
A system and method of driving a floating mass transducer with an analog input signal uIN(t), uIN(t) being between ground and VCC, is provided. The method includes converting uIN(t) to a binary rectangular signal uR(t) with two levels VCC and GND. A switching network is driven with uR(t) so as to switch nodes N1 and N2 between VCC and ground. The floating mass transducer is coupled between nodes N1 and N2 to a capacitor C in parallel, and further to a coil L in series.
摘要:
A stimulation system including a stimulator having a multi-channel electrode array utilizing a monopolar electrode configuration. A processor is operatively coupled to the stimulator. The processor is configured to determine a channel interaction (CI) sequence using simultaneous, sign-correlated pulses and channel interaction compensation. The CI sequence has a CI pulse rate and a CI mean pulse amplitude, and produces resulting potentials that are substantially equal to desired potentials at given positions relative to the multi-channel array. The CI sequence may include temporal gaps between pulses, wherein the processor may be configured to increase the CI pulse rate, such that the temporal gap between pulses is decreased. Furthermore, the processor may be configured to reduce the pulse amplitude of the CI sequence while increasing pulse phase duration, such that charge per pulse remains substantially unchanged and the temporal gap between pulses is decreased.
摘要:
An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range [−a+a]. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range [−b+b], wherein b
摘要:
An adaptive sigma delta modulator has an input stage, a conventional sigma delta modulator, and adaptation stage, and an output stage. The input stage produces a difference signal representing the difference between an analog input signal and an adaptive signal, the amplitude of the analog input signal being in a first range [−a+a]. The conventional sigma delta modulator produces an intermediate digital output sequence representative of the difference signal, the amplitude of the intermediate digital output sequence being in a second range [−b+b], wherein b
摘要:
A signal processing circuit is provided that includes a CMOS bridge rectifier circuit having a first input terminal and a second input terminal for receiving a rectangular wave form that includes a data sequence. A first output terminal and a second output terminal provides a rectified dc output voltage. A first data output terminal is connected to one of the first and the second input terminals, and a second data output terminal is connected to one of the first and the second output terminals, wherein the data output terminals provide an output signal representative of the data sequence. A substantially resistive load may be operatively coupled between the first and second voltage output terminals, the resistive load without a discrete parallel capacitor.