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公开(公告)号：US20160308553A1
公开(公告)日：2016-10-20
申请号：US15194420
申请日：2016-06-27
申请人： SOCIONEXT INC.
发明人： Yosuke MITANI , Takashi MORIE , Kazuo MATSUKAWA
摘要： Disclosed herein is an integrator including: a resistive element connected to an input terminal; an operational amplifier configured to receive, through the resistive element, an input signal that has been supplied to the input terminal; and a voltage regulator circuit connected to an intermediate node between the resistive element and the operational amplifier. The voltage regulator circuit has a first current source connected to the intermediate node, and a switch connected between the intermediate node and the first current source and selectively turning ON or OFF.
摘要翻译： 这里公开了一种积分器，包括：连接到输入端子的电阻元件; 运算放大器，被配置为通过电阻元件接收已经提供给输入端的输入信号; 以及连接到电阻元件和运算放大器之间的中间节点的电压调节器电路。 电压调节器电路具有连接到中间节点的第一电流源和连接在中间节点和第一电流源之间并且选择性地导通或关断的开关。
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公开(公告)号：US20140219384A1
公开(公告)日：2014-08-07
申请号：US14115566
申请日：2012-03-13
申请人： Shinichi Hori
发明人： Shinichi Hori
IPC分类号： H04L27/12
摘要： To provide a digital modulator including: a signal adjuster (105) which is provided with a plurality of output lines, and which outputs, to the output line, which corresponds to a range to which a level of an input signal belongs, a signal of a level corresponding to the level of the input signal; a plurality of internal digital modulators (111-1 to 111-N), each of which is provided so as to correspond to each of the plurality of output lines and carries out delta-sigma modulation on the signal of the corresponding output line to output the modulated signal; and an encoder (113) which encodes the plurality of modulated signals respectively outputted by the plurality of internal digital modulators.
摘要翻译： 提供一种数字调制器，包括：信号调节器（105），其设有多条输出线，并且输出到与输入信号的电平所属的范围相对应的输出线的信号 对应于输入信号电平的电平; 多个内部数字调制器（111-1至111-N），每个内部数字调制器（111-1至111-N）被提供以对应于多个输出线中的每一个，并对相应输出线的信号执行Δ-Σ调制以输出 调制信号; 以及对由多个内部数字调制器分别输出的多个调制信号进行编码的编码器（113）。
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公开(公告)号：US07590251B2
公开(公告)日：2009-09-15
申请号：US10805588
申请日：2004-03-19
CPC分类号： H03M3/48 , H03F1/523 , H03F3/2171 , H03F2200/331 , H03F2200/66 , H03G3/002 , H03G7/007 , H04L7/005 , H04L7/02
摘要： Systems and methods for detecting clipping conditions in an audio signal and processing the signal to reduce the clipping conditions. In one embodiment, a system comprises a noise shaper, a modulator, an output stage and other components. A detector detects clipping in the noise shaper and a signal processor processes the audio signal input to the noise shaper based on feedback received from the detector. The signal processor may function to modify the input audio signal in different ways in response to different conditions that are detected by the detector. A filter may be included to filter the output of the detector before being provided to the signal processor. A flag circuit may be coupled between the filter and the signal processor to assert an output signal until the signal processor resets the flag circuit.
摘要翻译： 用于检测音频信号中的限幅条件并处理信号以减少削波条件的系统和方法。 在一个实施例中，系统包括噪声整形器，调制器，输出级和其它组件。 检测器检测噪声整形器中的限幅，并且信号处理器基于从检测器接收到的反馈来处理输入到噪声整形器的音频信号。 响应于由检测器检测到的不同条件，信号处理器可以以不同的方式修改输入音频信号。 可以包括滤波器以在提供给信号处理器之前对检测器的输出进行滤波。 标志电路可以耦合在滤波器和信号处理器之间以断言输出信号，直到信号处理器复位标志电路。
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公开(公告)号：US20090072874A1
公开(公告)日：2009-03-19
申请号：US12097242
申请日：2006-12-02
申请人： Lars Sundstrom
发明人： Lars Sundstrom
IPC分类号： H03K5/02
摘要： This invention relates to adjusting a filter of a time-continuous Sigma-Delta converter arranged to convert an analog input signal (Sin) to a digital output signal. A control signal indicative of a gain of the filter is provided, and the gain of the filter is adjusted in dependence of the control signal. The control signal is provided from the digital output signal of the Sigma-Delta converter. In this way the performance of the Sigma-Delta converter can be improved in a simple way that requires no or few additional analog components, and the Sigma-Delta converter itself is used to adjust its performance. Using a signal from the digital domain of the Sigma-Delta converter is advantageous in that it is typically easier, faster and more precise to process signals in the digital domain.
摘要翻译： 本发明涉及调整时间连续Σ-Δ转换器的滤波器，其被布置为将模拟输入信号（Sin）转换成数字输出信号。 提供表示滤波器增益的控制信号，根据控制信号调整滤波器的增益。 控制信号由Sigma-Delta转换器的数字输出信号提供。 以这种方式，可以以不需要或少量额外的模拟组件的简单方式来改进Sigma-Delta转换器的性能，并且使用Sigma-Delta转换器本身来调整其性能。 使用来自Sigma-Delta转换器的数字域的信号是有利的，因为在数字域中处理信号通常更容易，更快速和更精确。
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5.发明授权Gain scaling for higher signal-to-noise ratios in multistage, multi-bit delta sigma modulators 有权在多级多位三角形Σ调制器中增益缩放以获得更高的信噪比公开(公告)号：US06750795B2
公开(公告)日：2004-06-15
申请号：US10043229
申请日：2002-01-14
申请人： Sandeep K. Gupta
发明人： Sandeep K. Gupta
IPC分类号： H03M300
摘要： Gain scaling of multistage, multi-bit delta sigma modulators for higher signal-to-noise ratios. In a multistage delta sigma modulator having a modulator stage with an integrator, a multi-bit quantizer, and a multi-bit digital-to-analog converter, the multi-bit quantizer is companded to cause a feedback signal, produced by the multi-bit digital-to-analog converter, to have a first gain, with respect to an integrated signal received by the multi-bit quantizer, set greater than one. A second gain, of the integrator, is reduced so that an overall gain of the modulator stage remains equal to one. A third gain, of a stability correction gain element connected to an input of the modulator stage, is increased so that a swing of the integrated signal remains within a dynamic range of an operational amplifier used to implement the integrator, and the multistage delta sigma modulator can realize the higher signal-to-noise ratio.
摘要翻译： 增加多级，多位三角形Σ调制器的缩放比例，提高信噪比。 在具有具有积分器，多位量化器和多位数模转换器的调制器级的多级Δ-Σ调制器中，多比特量化器被压缩以产生由多位数模转换器产生的反馈信号， 相对于由多位量化器接收的积分信号，具有大于1的第一增益。 积分器的第二增益被减小，使得调制器级的总体增益保持等于1。 连接到调制器级的输入的稳定性校正增益元件的第三增益被增加，使得积分信号的摆动保持在用于实现积分器的运算放大器的动态范围内，并且多级Δ-Σ调制器 可以实现更高的信噪比。
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6.发明申请Gain scaling for higher signal-to-noise ratios in multistage, multi-bit delta sigma modulators 失效在多级多位三角形Σ调制器中增益缩放以获得更高的信噪比公开(公告)号：US20030085826A1
公开(公告)日：2003-05-08
申请号：US10326706
申请日：2002-12-23
申请人： Broadcom Corporation
发明人： Sandeep K. Gupta
IPC分类号： H03M003/02
摘要： An n-bit quantizer of a downstream modulator stage is configured to produce an n-bit quantized signal from an analog signal having a range. The n-bit quantizer divides the range into 2n subranges. A first subrange of the 2n subranges is bounded by a lowest value of the range, a second subrange of the 2n subranges is bounded by a highest value of the range, and at least one remaining subrange of the 2n subranges is positioned between the first and the second subranges. The first and the second subranges each measure greater than null1/null2(2nnull1)nullnull of the total range. Each of the at least one remaining subrange measures less than null1/(2nnull1)null of the total range. A first gain of an integrator of the downstream modulator stage is set so that the downstream modulator stage is stable. A second gain of a stability correction gain element of a coupling stage connected to the downstream modulator is set so that a swing of the analog signal remains within a dynamic range of the downstream modulator stage.
摘要翻译： 下行调制级的n位量化器被配置为从具有范围的模拟信号产生n位量化信号。 n位量化器将范围分为2n个子范围。 2n个子范围的第一子范围由该范围的最低值界定，2n个子范围的第二子范围由该范围的最大值限定，并且2n个子范围的至少一个剩余子范围位于第一和第 第二个次级 第一和第二子范围大于总范围的{1 / [2（2n-1）]}。 每个至少一个剩余子范围测量值小于总范围的[1 /（2n-1）]。 设置下游调制器级的积分器的第一增益，使得下游调制器级稳定。 设置连接到下游调制器的耦合级的稳定性校正增益元件的第二增益，使得模拟信号的摆幅保持在下游调制器级的动态范围内。
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公开(公告)号：US09100032B2
公开(公告)日：2015-08-04
申请号：US14453407
申请日：2014-08-06
CPC分类号： H03M1/0619 , H03M1/129 , H03M1/181 , H03M1/187 , H03M3/48 , H03M3/49 , H03M3/492 , H04R3/00 , H04R2410/00
摘要： Analog-to-digital converter arrangements and corresponding methods are provided, wherein a reduction signal is subtracted from an analog input signal if a signal level of the input signal exceeds a threshold value.
摘要翻译： 提供了模数转换器布置和相应的方法，其中如果输入信号的信号电平超过阈值，则从模拟输入信号中减去减少信号。
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公开(公告)号：US20150042496A1
公开(公告)日：2015-02-12
申请号：US14453407
申请日：2014-08-06
CPC分类号： H03M1/0619 , H03M1/129 , H03M1/181 , H03M1/187 , H03M3/48 , H03M3/49 , H03M3/492 , H04R3/00 , H04R2410/00
摘要： Analog-to-digital converter arrangements and corresponding methods are provided, wherein a reduction signal is subtracted from an analog input signal if a signal level of the input signal exceeds a threshold value.
摘要翻译： 提供了模数转换器布置和相应的方法，其中如果输入信号的信号电平超过阈值，则从模拟输入信号中减去减少信号。
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9.发明申请ANALOG-TO-DIGITAL CONVERTER FOR CONTROLLING GAIN BY CHANGING A SYSTEM PARAMETER, IMAGE SENSOR INCLUDING THE ANALOG-TO-DIGITAL CONVERTER AND METHOD OF OPERATING THE ANALOG-TO-DIGITAL CONVERTER 有权用于通过更改系统参数控制增益的模拟数字转换器，包括模拟数字转换器的图像传感器和操作模数转换器的方法公开(公告)号：US20110069211A1
公开(公告)日：2011-03-24
申请号：US12879684
申请日：2010-09-10
申请人： Wun-Ki JUNG , Seog Heon HAM , Dong Hun LEE , Kwi Sung YOO , Min Ho KWON
发明人： Wun-Ki JUNG , Seog Heon HAM , Dong Hun LEE , Kwi Sung YOO , Min Ho KWON
摘要： Example embodiments are directed to an analog-to-digital converter (ADC) that controls a gain by changing a system parameter, an image sensor including the ADC and a method of operating the ADC. The ADC includes a sigma-delta modulator which receives an input signal and a clock signal and sigma-delta modulates the input signal into a digital output signal based on the clock signal and an accumulation unit which accumulates the digital output signal at each cycle of the clock signal according to an analog-to-digital conversion time and outputs an accumulation result. A system parameter is varied during the analog-to-digital conversion time to control a gain of the ADC. The method of operating the analog-to-digital converter includes sigma-delta modulating an input signal into a digital output signal in response to a clock signal input to the ADC; and accumulating the digital output signal at each cycle of the input clock signal according to an analog-to-digital conversion time and outputting an accumulation result.
摘要翻译： 示例性实施例针对通过改变系统参数来控制增益的模数转换器（ADC），包括ADC的图像传感器和操作ADC的方法。 ADC包括Σ-Δ调制器，其接收输入信号和时钟信号，并且Σ-Δ基于时钟信号将输入信号调制成数字输出信号;以及累积单元，其在每个周期的每个周期累积数字输出信号 时钟信号，并输出累积结果。 在模数转换时间期间，系统参数会发生变化，以控制ADC的增益。 操作模数转换器的方法包括响应于输入到ADC的时钟信号而将输入信号Σ-Δ调制成数字输出信号; 并且根据模数转换时间在输入时钟信号的每个周期累加数字输出信号，并输出累加结果。
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公开(公告)号：US07880652B2
公开(公告)日：2011-02-01
申请号：US12097242
申请日：2006-12-02
申请人： Lars Sundström
发明人： Lars Sundström
IPC分类号： H03M1/62
摘要： This invention relates to adjusting a filter of a time-continuous Sigma-Delta converter arranged to convert an analog input signal (Sin) to a digital output signal. A control signal indicative of a gain of the filter is provided, and the gain of the filter is adjusted in dependence of the control signal. The control signal is provided from the digital output signal of the Sigma-Delta converter. In this way the performance of the Sigma-Delta converter can be improved in a simple way that requires no or few additional analog components, and the Sigma-Delta converter itself is used to adjust its performance. Using a signal from the digital domain of the Sigma-Delta converter is advantageous in that it is typically easier, faster and more precise to process signals in the digital domain.
摘要翻译： 本发明涉及调整时间连续Σ-Δ转换器的滤波器，其被布置为将模拟输入信号（Sin）转换成数字输出信号。 提供表示滤波器增益的控制信号，根据控制信号调整滤波器的增益。 控制信号由Sigma-Delta转换器的数字输出信号提供。 以这种方式，可以以不需要或少量额外的模拟组件的简单方式来改进Sigma-Delta转换器的性能，并且使用Sigma-Delta转换器本身来调整其性能。 使用来自Sigma-Delta转换器的数字域的信号是有利的，因为在数字域中处理信号通常更容易，更快速和更精确。
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