中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.017 seconds)

    Memory addressing
    1.
    发明授权
    Memory addressing 有权
    内存寻址

    公开(公告)号：US07401202B1

    公开(公告)日：2008-07-15

    申请号：US11227423

    申请日：2005-09-14

    Applicant: Cliff N. Click, Jr.

    Inventor： Cliff N. Click, Jr.

    IPC: G06F9/25 ,  G06F9/34

    CPC classification number: G06F8/315 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/345 ,  G06F9/355 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/461

    Abstract: Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand to provide a shifted, sign-extended operand, and adding the shifted, sign-extended operand to the second operand. The second operand has a different bit length than the first operand.

    Abstract translation: 寻址存储器包括：向存储器寻址操作器接收第一操作数，向存储器寻址操作器接收第二操作数，在第一操作数上执行符号扩展以提供符号扩展操作数，移位符号扩展操作数以提供移位符号 扩展的操作数，并将移位的符号扩展操作数添加到第二个操作数。 第二个操作数具有与第一个操作数不同的位长度。

    Array access
    2.
    发明授权
    Array access 有权
    阵列访问

    公开(公告)号：US07577801B1

    公开(公告)日：2009-08-18

    申请号：US11296191

    申请日：2005-12-06

    Applicant: Gil Tene ,  Jack H. Choquette ,  Scott Sellers ,  Cliff N. Click, Jr.

    Inventor： Gil Tene ,  Jack H. Choquette ,  Scott Sellers ,  Cliff N. Click, Jr.

    IPC: G06F12/02

    CPC classification number: G06F12/0223 ,  G06F9/30043 ,  G06F9/345

    Abstract: Accessing memory in an array includes performing a first instruction, including by determining whether an index used by the first instruction is within a valid range and in the event that the index is within a valid range, determining a memory address related to an array element that corresponds to the index. Accessing memory in the array further includes, in the event that the index is within a valid range, performing a second instruction to access the array element, the access being based at least in part on the memory address determined by the first instruction.

    Abstract translation: 访问阵列中的存储器包括执行第一指令，包括通过确定第一指令使用的索引是否在有效范围内，以及在索引在有效范围内的情况下，确定与阵列元素有关的存储器地址， 对应于索引。 如果索引在有效范围内，执行第二指令来访问数组元素，访问存储器还包括至少部分地基于由第一指令确定的存储器地址的访问。

    Accelerated class check
    3.
    发明授权
    Accelerated class check 有权
    加速班级检查

    公开(公告)号：US08839274B2

    公开(公告)日：2014-09-16

    申请号：US13227111

    申请日：2011-09-07

    Applicant: Gil Tene ,  Cliff N. Click, Jr. ,  Murali Sundaresan ,  Michael A. Wolf

    Inventor： Gil Tene ,  Cliff N. Click, Jr. ,  Murali Sundaresan ,  Michael A. Wolf

    IPC: G06F9/54 ,  G06F9/30 ,  G06F9/44

    CPC classification number: G06F9/4428 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/4488 ,  G06F9/449 ,  G06F9/455

    Abstract: Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.

    Abstract translation: 处理虚拟方法调用包括从对象的指针提取与对象的类相关联的标识符，与虚拟方法调用相关联的对象的指针，以及嵌入在指针内的标识符; 使用所述标识符来获得虚拟方法表，包括将映射多个类标识符的类标识符表中的第一条目定位到对应的多个类数据，所述第一条目与所述标识符相关联，并且包括所述虚方法表或 指针用于获取虚拟方法表; 在虚拟方法表中定位第二条目，第二条目与虚拟方法调用相关联; 并跳转到与第二条目相关联的地址，以在该地址处执行代码。

    Garbage collection barrier with direct user mode traps
    6.
    发明授权
    Garbage collection barrier with direct user mode traps 有权
    垃圾收集障碍与直接用户模式陷阱

    公开(公告)号：US08046544B2

    公开(公告)日：2011-10-25

    申请号：US12592579

    申请日：2009-11-25

    Applicant: Cliff N. Click, Jr. ,  Gil Tene ,  Michael A. Wolf

    Inventor： Cliff N. Click, Jr. ,  Gil Tene ,  Michael A. Wolf

    IPC: G06F13/00

    CPC classification number: G06F12/0269

    Abstract: A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a set of garbage collection instructions configured to perform one or more garbage collection barrier operations and a subsequent instruction that immediately follows the garbage collection instruction; wherein the processor is configured to execute the set of garbage collection instructions, including by: evaluating a memory reference to determine a condition associated with the set of garbage collection instructions; and in the event that the condition is met, while maintaining the same privilege level, saving information that is based at least in part on the current value of a program counter, and setting the program counter to correspond to a target location that is other than the location of the subsequent instruction.

    Abstract translation: 计算机系统包括处理器; 以及耦合到所述处理器的存储器，被配置为向所述处理器提供多个指令，所述指令包括被配置为执行一个或多个垃圾收集屏障操作的一组垃圾收集指令以及紧随所述垃圾收集指令的后续指令; 其中所述处理器被配置为执行所述一组垃圾收集指令，包括：评估存储器引用以确定与所述一组垃圾收集指令相关联的条件; 并且在条件满足的情况下，在保持相同特权级别的情况下，至少部分地基于程序计数器的当前值保存信息，并且将程序计数器设置为对应于除 后续指令的位置。

    Garbage collection
    7.
    发明授权
    Garbage collection 有权
    垃圾收集

    公开(公告)号：US07647458B1

    公开(公告)日：2010-01-12

    申请号：US12082239

    申请日：2008-04-08

    Applicant: Cliff N. Click, Jr. ,  Gil Tene ,  Michael A. Wolf

    Inventor： Cliff N. Click, Jr. ,  Gil Tene ,  Michael A. Wolf

    IPC: G06F12/00

    CPC classification number: G06F12/0269

    Abstract: A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a garbage collection barrier instruction and a subsequent instruction that immediately follows the garbage collection barrier instruction; wherein the processor is configured to execute the garbage collection barrier instruction, including by: evaluating a memory reference to determine a condition associated with the garbage collection barrier instruction; and in the event that the condition is met, while maintaining the same privilege level, saving information that is based at least in part on the current value of a program counter, and setting the program counter to correspond to a target location that is other than the location of the subsequent instruction.

    Abstract translation: 计算机系统包括处理器; 以及耦合到所述处理器的存储器，被配置为向所述处理器提供包括垃圾收集屏障指令和紧随在所述垃圾收集屏障指令之后的随后指令的多个指令; 其中所述处理器被配置为执行所述垃圾回收障碍指令，包括：评估存储器引用以确定与所述垃圾收集屏障指令相关联的条件; 并且在条件满足的情况下，在保持相同特权级别的情况下，至少部分地基于程序计数器的当前值保存信息，并且将程序计数器设置为对应于除 后续指令的位置。

    Detecting and recording atomic execution
    8.
    发明授权
    Detecting and recording atomic execution 有权

    公开(公告)号：US09928072B1

    公开(公告)日：2018-03-27

    申请号：US12387478

    申请日：2009-05-01

    Applicant: Gil Tene ,  Michael A. Wolf ,  Cliff N. Click, Jr.

    Inventor： Gil Tene ,  Michael A. Wolf ,  Cliff N. Click, Jr.

    IPC: G06F9/30 ,  G06F9/38 ,  G06F11/36

    CPC classification number: G06F9/3842 ,  G06F9/30 ,  G06F11/3636

    Abstract: A system includes a processor configured to: initiate atomic execution of a plurality of instruction units in a thread, starting with a beginning instruction unit in the plurality of instruction units, wherein the plurality of instruction units is not programmatically specified to be executed atomically; detect an atomicity terminating event during atomic execution of the plurality of instruction units, wherein the atomicity terminating event is triggered by a memory access by another processor; and establish an incidentally atomic sequence of instruction units based at least in part on detection of the atomicity terminating event, wherein the incidentally atomic sequence of instruction units correspond to a sequence of instruction units in the plurality of instruction units. The system further includes a memory coupled to the processor, configured to provide the processor with the plurality of instruction units.

    CPU utilization metering on systems that include multiple hardware threads per core
    9.
    发明授权
    CPU utilization metering on systems that include multiple hardware threads per core 有权
    每个核心包含多个硬件线程的系统上的CPU利用率测量

    公开(公告)号：US08838940B2

    公开(公告)日：2014-09-16

    申请号：US11449154

    申请日：2006-06-07

    Applicant: Gil Tene ,  Michael A. Wolf ,  Cliff N. Click, Jr.

    Inventor： Gil Tene ,  Michael A. Wolf ,  Cliff N. Click, Jr.

    IPC: G06F15/00 ,  G06F9/30 ,  G06F9/44 ,  G06F11/34

    CPC classification number: G06F11/3409 ,  G06F11/3423 ,  G06F2201/88

    Abstract: Indicating usage in a system is disclosed. Indicating includes obtaining active thread information related to a number of hardware threads in a processor core, combining the active thread information with information related to a decreasing ability of the processor core to increase throughput by utilizing additional hardware threads, and indicating the usage in the system based at least in part on both the active thread information and the ability of the processor core to increase throughput by utilizing additional hardware threads.

    Abstract translation: 披露了系统中的使用情况。 指示包括获得与处理器核心中的多个硬件线程相关的活动线程信息，将活动线程信息与与处理器核心的降低能力相关的信息组合以通过利用附加硬件线程来增加吞吐量，并指示系统中的使用 至少部分地基于活动线程信息和处理器核心通过利用附加硬件线程来增加吞吐量的能力。

Patent Agency Ranking