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19 条记录 (耗时 0.035 秒)

    On-chip repair of defective address of core flash memory cells
    1.
    发明授权
    On-chip repair of defective address of core flash memory cells 有权
    核心闪存单元故障地址的片上修复

    公开(公告)号：US06631086B1

    公开(公告)日：2003-10-07

    申请号：US10200544

    申请日：2002-07-22

    申请人： Colin Bill ,  Ken Cheong Cheah ,  Edward V. Bautista, Jr. ,  Azrul Halim ,  Darlene G. Hamilton

    发明人： Colin Bill ,  Ken Cheong Cheah ,  Edward V. Bautista, Jr. ,  Azrul Halim ,  Darlene G. Hamilton

    IPC分类号： G11C1606

    CPC分类号： G11C29/72 ,  G11C15/00 ,  G11C16/04 ,  G11C29/16 ,  G11C29/44 ,  G11C29/48

    摘要： In a method and system for repairing defective flash memory cells fabricated on a semiconductor substrate, a repair controller and a plurality of voltage sources are fabricated on the semiconductor substrate. The repair controller controls the voltage sources to apply programming voltages on respective CAM (content addressable memory) flash memory cells in a JUICE state for replacing the defective flash memory cells with a corresponding redundancy element of flash memory cells. In addition, a FAILREP logic is fabricated on the semiconductor substrate for entering a HANG state if no redundancy element of flash memory cells is available or if the defective flash memory cells have been previously repaired.

    摘要翻译： 在用于修复在半导体衬底上制造的有缺陷的闪速存储器单元的方法和系统中，在半导体衬底上制造修复控制器和多个电压源。 修理控制器控制电压源以将编程电压施加在JUICE状态的相应CAM（内容可寻址存储器）闪存单元上，以用闪存单元的相应冗余元件代替有缺陷的闪存单元。 此外，如果没有闪存单元的冗余元件可用或者有缺陷的闪速存储器单元已经被修复，则在半导体衬底上制造FAILREP逻辑用于进入HANG状态。

    Diagnostic mode for testing functionality of BIST (built-in-self-test) back-end state machine
    3.
    发明授权
    Diagnostic mode for testing functionality of BIST (built-in-self-test) back-end state machine 有权
    用于测试BIST（内置自检）后端状态机的功能的诊断模式

    公开(公告)号：US07028240B1

    公开(公告)日：2006-04-11

    申请号：US10200526

    申请日：2002-07-22

    申请人： Edward V. Bautista, Jr. ,  Ken Cheong Cheah ,  Colin Bill

    发明人： Edward V. Bautista, Jr. ,  Ken Cheong Cheah ,  Colin Bill

    IPC分类号： G01R3/28

    CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/16

    摘要： In a method and system for diagnosing a back-end state machine used for testing flash memory cells fabricated on a semiconductor substrate, a signal selector and a diagnostic matching logic are fabricated on the semiconductor substrate. The diagnostic matching logic sets a generated match output to a pass or fail state depending on control variables from the back-end state machine. The signal selector selects the generated match output to be used in a verify step of a BIST (built-in-self-test) mode, if a diagnostic mode is invoked. The back-end state machine performs a plurality of BIST modes with the generated match output, for testing the functionality of the back-end state machine.

    摘要翻译： 在用于诊断用于测试在半导体衬底上制造的闪存单元的后端状态机的方法和系统中，在半导体衬底上制造信号选择器和诊断匹配逻辑。 诊断匹配逻辑根据后端状态机的控制变量将生成的匹配输出设置为通过或失败状态。 如果调用诊断模式，则信号选择器选择要在BIST（内置自检）模式的验证步骤中使用的生成的匹配输出。 后端状态机利用生成的匹配输出执行多个BIST模式，用于测试后端状态机的功能。

    CAM (content addressable memory) cells as part of core array in flash memory device
    4.
    发明授权
    CAM (content addressable memory) cells as part of core array in flash memory device 有权
    CAM（内容可寻址存储器）单元作为闪存设备中的核心阵列的一部分

    公开(公告)号：US06970368B1

    公开(公告)日：2005-11-29

    申请号：US10650049

    申请日：2003-08-26

    申请人： Edward V. Bautista, Jr. ,  Ken Cheong Cheah

    发明人： Edward V. Bautista, Jr. ,  Ken Cheong Cheah

    IPC分类号： G11C15/00 ,  G11C15/04

    CPC分类号： G11C15/046

    摘要： In a method and system for providing a CAM (content addressable memory) cell of a flash memory device, a respective core flash memory cell to be used as the CAM cell is fabricated as part of a core array of the flash memory device. In addition, the respective core flash memory cell is accessed from the core array as the CAM cell for a CAM function within the flash memory device. Components used for supporting operation of the core array are also used for accessing the core flash memory cells of the additional sector for such CAM functionality. Thus, CAM functionality is provided with a minimized number of components and with minimized area of the die of the flash memory device. In addition, because the CAM cells are implemented as core flash memory cells of the core array, the CAM cells may reliably undergo more numerous programming and erasing cycles.

    摘要翻译： 在用于提供闪速存储器件的CAM（内容可寻址存储器）单元的方法和系统中，将要用作CAM单元的相应核心闪速存储器单元制造为闪速存储器件的核心阵列的一部分。 此外，各个核心闪存单元从核心阵列作为用于CAM存储器件内的CAM功能的CAM单元访问。 用于支持核心阵列操作的组件也用于访问用于这种CAM功能的附加扇区的核心闪存单元。 因此，CAM功能被提供有最少数量的部件并且具有闪存器件的管芯的最小面积。 另外，由于CAM单元被实现为核心阵列的核心闪存单元，因此CAM单元可以可靠地进行更多的编程和擦除周期。

    On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode
    5.
    发明授权
    On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode 有权
    片内擦除脉冲计数器，用于高效擦除验证BIST（内置自检）模式

    公开(公告)号：US06665214B1

    公开(公告)日：2003-12-16

    申请号：US10200330

    申请日：2002-07-22

    申请人： Ken Cheong Cheah ,  Edward V. Bautista, Jr. ,  Weng Fook Lee ,  Boon Tang Teh

    发明人： Ken Cheong Cheah ,  Edward V. Bautista, Jr. ,  Weng Fook Lee ,  Boon Tang Teh

    IPC分类号： G11C1606

    CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/02 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/5002

    摘要： In a method and system for monitoring erase pulses applied on a sector of flash memory cells fabricated on a semiconductor substrate, a pulse counter and a pulse counter controller are fabricated on the semiconductor substrate. The pulse counter controller inputs a maximum number and outputs an indication of a sector fail if the flash memory cells of the sector do not pass erase verification with less than the maximum number of erase pulses applied on the sector during an erase verify BIST (Built-in-Self-Test) mode. In one example, the maximum number is a percentage of a diagonal total number of erase pulses needed to be applied on the sector until each flash memory cell at a diagonal location of the sector passes erase verification.

    摘要翻译： 在用于监视施加在制造在半导体衬底上的快闪存储器单元的扇区上的擦除脉冲的方法和系统中，在半导体衬底上制造脉冲计数器和脉冲计数器控制器。 脉冲计数器控制器输入最大数量，并且如果在擦除验证期间扇区的闪速存储单元不通过小于刷新扇区上最大擦除脉冲数的擦除验证，则输出扇区失败的指示BIST（Built- 自检）模式。 在一个示例中，最大数量是需要施加在扇区上的擦除脉冲的对角线总数的百分比，直到扇区的对角线位置处的每个闪存单元通过擦除验证。

    Memory device and method
    6.
    发明授权
    Memory device and method 有权
    内存设备和方法

    公开(公告)号：US06980473B1

    公开(公告)日：2005-12-27

    申请号：US10677031

    申请日：2003-10-01

    申请人： Edward V. Bautista, Jr. ,  Ken Cheong Cheah ,  Chi-Mun Ho

    发明人： Edward V. Bautista, Jr. ,  Ken Cheong Cheah ,  Chi-Mun Ho

    IPC分类号： G11C16/04 ,  G11C16/12 ,  G11C16/30 ,  G11C16/34

    CPC分类号： G11C16/3459 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3454 ,  G11C29/021 ,  G11C29/028

    摘要： A memory device and a method for compensating for a load current in the memory device. The memory device includes a plurality of I/O buffers where each I/O buffer includes an I/O write-buffer driver circuit. The I/O write-buffer driver circuit is coupled to a load current compensation circuit. Although each I/O buffer includes an I/O write-buffer circuit, a single load current compensation circuit may be coupled to several I/O write-buffer driver circuits. The load current compensation circuit generates a load compensation current for each I/O buffer circuit that is not being programmed. The load compensation current increases the load current so that a drain-side programming voltage (VPROG) drives a substantially constant load current, wherein the drain-side programming voltage is substantially independent of the number of bits being programmed.

    摘要翻译： 一种用于补偿存储器件中的负载电流的存储器件和方法。 存储器件包括多个I / O缓冲器，其中每个I / O缓冲器包括I / O写缓冲器驱动电路。 I / O写缓冲器驱动电路耦合到负载电流补偿电路。 尽管每个I / O缓冲器都包含一个I / O写缓冲电路，但单个负载电流补偿电路可以耦合到多个I / O写缓冲器驱动电路。 负载电流补偿电路为未编程的每个I / O缓冲电路产生负载补偿电流。 负载补偿电流增加负载电流，使得漏极侧编程电压（VPROG）驱动基本恒定的负载电流，其中漏极侧编程电压基本上与被编程的位数无关。

    Memory device and method
    8.
    发明授权
    Memory device and method 有权
    内存设备和方法

    公开(公告)号：US06973003B1

    公开(公告)日：2005-12-06

    申请号：US10677073

    申请日：2003-10-01

    申请人： Syahrizal Salleh ,  Edward V. Bautista, Jr. ,  Ken Cheong Cheah

    发明人： Syahrizal Salleh ,  Edward V. Bautista, Jr. ,  Ken Cheong Cheah

    IPC分类号： G11C7/00 ,  G11C11/406

    CPC分类号： G11C11/40622 ,  G11C11/406

    摘要： A memory device and a method for refreshing the memory device. The memory device includes a memory cell capable of storing two bits of data. One bit is referred to as the normal data bit and the other bit is referred to as the complementary data bit. Each memory cell has an associated dynamic reference cell. The normal data is refreshed by latching refresh data into a data latch and ORing the latched data with input data. The refresh data is written to the corresponding memory location. The data for the complementary data bit is refreshed by latching complementary data bit refresh data into the complementary data latches and writing to the memory cell. The normal and complementary data bits are refreshed before each read operation.

    摘要翻译： 一种用于刷新存储器件的存储器件和方法。 存储器件包括能够存储两位数据的存储器单元。 一位被称为正常数据位，另一位称为互补数据位。 每个存储单元具有相关联的动态参考单元。 正常数据通过将刷新数据锁存到数据锁存器中并将锁存数据与输入数据进行OR运算来刷新。 刷新数据被写入相应的存储单元。 通过将互补数据位刷新数据锁存到互补数据锁存器中并写入存储单元来刷新补充数据位的数据。 正常和互补的数据位在每次读取操作之前刷新。

    Method and system for embedded chip erase verification
    9.
    发明授权
    Method and system for embedded chip erase verification 有权
    嵌入式芯片擦除验证方法和系统

    公开(公告)号：US06331951B1

    公开(公告)日：2001-12-18

    申请号：US09717550

    申请日：2000-11-21

    申请人： Edward V. Bautista, Jr. ,  Darlene G. Hamilton ,  Weng Fook Lee ,  Pau-Ling Chen ,  Keith H. Wong

    发明人： Edward V. Bautista, Jr. ,  Darlene G. Hamilton ,  Weng Fook Lee ,  Pau-Ling Chen ,  Keith H. Wong

    IPC分类号： G11C1606

    CPC分类号： G11C16/344 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3445

    摘要： A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.

    摘要翻译： 公开了用于验证存储器单元擦除的方法和系统，其可以与双位存储器单元架构相关联使用。 该方法包括选择性地验证小区的第一比特和小区的第二比特之一的适当擦除，如果小区的第一和第二比特被正确擦除，则确定双比特存储单元被适当地擦除，并且选择性地擦除 如果第一和第二位之一没有被正确擦除，则单元的第一和第二位中的至少一个位。 该方法还可以包括在选择性地擦除第一和第二比特中的至少一个之后，选择性地重新验证第一和第二比特之一的适当擦除。