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    Method of programming, reading and erasing memory-diode in a memory-diode array
    1.
    发明申请
    Method of programming, reading and erasing memory-diode in a memory-diode array 有权
    在存储二极管阵列中编程，读取和擦除存储二极管的方法

    公开(公告)号：US20060139994A1

    公开(公告)日：2006-06-29

    申请号：US11021958

    申请日：2004-12-23

    申请人： Colin Bill ,  Swaroop Kaza ,  Tzu-Ning Fang ,  Stuart Spitzer

    发明人： Colin Bill ,  Swaroop Kaza ,  Tzu-Ning Fang ,  Stuart Spitzer

    IPC分类号： G11C11/36

    CPC分类号： G11C11/36

    摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.

    摘要翻译： 存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。 在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。 在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。 每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。 通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

    Method of programming, reading and erasing memory-diode in a memory-diode array
    2.
    发明授权
    Method of programming, reading and erasing memory-diode in a memory-diode array 有权
    在存储二极管阵列中编程，读取和擦除存储二极管的方法

    公开(公告)号：US07379317B2

    公开(公告)日：2008-05-27

    申请号：US11021958

    申请日：2004-12-23

    申请人： Colin S. Bill ,  Swaroop Kaza ,  Tzu-Ning Fang ,  Stuart Spitzer

    发明人： Colin S. Bill ,  Swaroop Kaza ,  Tzu-Ning Fang ,  Stuart Spitzer

    IPC分类号： G11C5/06 ,  G11C17/06

    CPC分类号： G11C11/36

    摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.

    摘要翻译： 存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。 在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。 在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。 每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。 通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

    Memory element using active layer of blended materials
    4.
    发明授权
    Memory element using active layer of blended materials 有权
    记忆元素使用有源层的混合材料

    公开(公告)号：US07378682B2

    公开(公告)日：2008-05-27

    申请号：US11052688

    申请日：2005-02-07

    申请人： David Gaun ,  Swaroop Kaza ,  Stuart Spitzer ,  Juri Krieger ,  Richard Kingsborough

    发明人： David Gaun ,  Swaroop Kaza ,  Stuart Spitzer ,  Juri Krieger ,  Richard Kingsborough

    IPC分类号： H01L51/00

    CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016

    摘要： The present memory device has first and second electrodes, a passive layer between the first and second electrodes and on and in contact with the first electrode, and an active layer between the first and second electrodes and on and in contact with the passive layer and second electrode, for receiving a charged specie from the passive layer. The active layer is a mixture of (i) a first polymer, and (ii) a second polymer for enhancing ion transport, improving the interface and promoting a rapid and substantially uniform distribution of the charged specie in the active layer, i.e., preventing a localized injection of the charged species. These features result in a memory element with improved stability, a more controllable ON-state resistance, improved switching speed and a lower programming voltage.

    摘要翻译： 本存储器件具有第一和第二电极，在第一和第二电极之间并且与第一电极接触并且与第一电极接触的无源层以及在第一和第二电极之间并且与被动层和第二电极接触的有源层 电极，用于从被动层接收带电物质。 活性层是（i）第一聚合物和（ii）用于增强离子迁移的第二聚合物的混合物，改善界面并促进活性层中带电物质的快速且基本上均匀的分布，即防止 局部注射带电物种。 这些特征导致存储元件具有改进的稳定性，更可控的导通电阻，改进的开关速度和较低的编程电压。

    Memory element using active layer of blended materials
    7.
    发明申请
    Memory element using active layer of blended materials 有权
    记忆元素使用有源层的混合材料

    公开(公告)号：US20060175646A1

    公开(公告)日：2006-08-10

    申请号：US11052688

    申请日：2005-02-07

    申请人： David Gaun ,  Swaroop Kaza ,  Stuart Spitzer ,  Juri Krieger ,  Richard Kingsborough

    发明人： David Gaun ,  Swaroop Kaza ,  Stuart Spitzer ,  Juri Krieger ,  Richard Kingsborough

    IPC分类号： H01L29/94

    CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016

    摘要： The present memory device has first and second electrodes, a passive layer between the first and second electrodes and on and in contact with the first electrode, and an active layer between the first and second electrodes and on and in contact with the passive layer and second electrode, for receiving a charged specie from the passive layer. The active layer is a mixture of (i) a first polymer, and (ii) a second polymer for enhancing ion transport, improving the interface and promoting a rapid and substantially uniform distribution of the charged specie in the active layer, i.e., preventing a localized injection of the charged species. These features result in a memory element with improved stability, a more controllable ON-state resistance, improved switching speed and a lower programming voltage.

    摘要翻译： 本存储器件具有第一和第二电极，在第一和第二电极之间并且与第一电极接触并且与第一电极接触的无源层以及在第一和第二电极之间并且与被动层和第二电极接触的有源层 电极，用于从被动层接收带电物质。 活性层是（i）第一聚合物和（ii）用于增强离子迁移的第二聚合物的混合物，改善界面并促进活性层中带电物质的快速且基本上均匀的分布，即防止 局部注射带电物种。 这些特征导致存储元件具有改进的稳定性，更可控的导通电阻，改进的开关速度和较低的编程电压。

    Memory device including barrier layer for improved switching speed and data retention
    10.
    发明授权
    Memory device including barrier layer for improved switching speed and data retention 有权
    存储器件包括用于提高开关速度和数据保持的阻挡层

    公开(公告)号：US07154769B2

    公开(公告)日：2006-12-26

    申请号：US11052689

    申请日：2005-02-07

    申请人： Juri Krieger ,  Stuart Spitzer

    发明人： Juri Krieger ,  Stuart Spitzer

    IPC分类号： G11C11/00

    CPC分类号： H01L45/12 ,  G11C13/0009 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/51 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146

    摘要： The present memory device includes a first electrode, a passive layer on and in contact with the first electrode, the passive layer including copper sulfide, a barrier layer on and in contact with the passive layer, an active layer on and in contact with the barrier layer, and a second electrode on and in contact with the active layer. The inclusion of the barrier layer in this environment increases switching speed of the memory device, while also improving data retention thereof.

    摘要翻译： 本存储器件包括第一电极，与第一电极接触并与第一电极接触的钝化层，钝化层包括硫化铜，与钝化层接触并与其接触的阻挡层，与屏障接触并与屏障接触的有源层 层，以及与活性层接触并与活性层接触的第二电极。 在该环境中包含阻挡层增加了存储器件的切换速度，同时也提高了其数据保持性。