公开(公告)号：US07273766B1

公开(公告)日：2007-09-25

申请号：US11034071

申请日：2005-01-12

申请人： Zhida Lan ,  Michael A. Van Buskirk ,  Tzu-Ning Fang ,  Colin Bill ,  John S. Ennals

发明人： Zhida Lan ,  Michael A. Van Buskirk ,  Tzu-Ning Fang ,  Colin Bill ,  John S. Ennals

IPC分类号： H01L21/00

CPC分类号： H01L27/285 ,  G11C11/5664 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0035 ,  G11C13/0061 ,  G11C13/0069 ,  G11C14/00 ,  G11C2213/55 ,  G11C2213/71

摘要： An organic memory device comprising two electrodes having a selectively conductive decay media between the two electrodes provides a capability to control a persistence level for information stored in an organic memory cell. A resistive state of the cell controls a conductive decay rate of the cell. A high and/or low resistive state can provide a fast and/or slow rate of conductive decay. One aspect of the present invention can have a high resistive state equating to an exponential conductive decay rate. Another aspect of the present invention can have a low resistive state equating to a logarithmic conductive decay rate. Yet another aspect relates to control of an organic memory device by determining a power state and setting a resistive state of an organic memory cell based upon a current power state and/or an imminent power state.

摘要翻译： 包括在两个电极之间具有选择性导电衰减介质的两个电极的有机存储器件提供了控制存储在有机存储器单元中的信息的持久性水平的能力。 电池的电阻状态控制电池的导电衰减速率。 高和/或低电阻状态可以提供快速和/或慢速的导电衰减。 本发明的一个方面可以具有等于指数导电衰减速率的高电阻状态。 本发明的另一方面可以具有等于对数导电衰减速率的低电阻状态。 另一方面涉及通过基于当前功率状态和/或迫在眉睫的功率状态确定有功存储器单元的功率状态和设置电阻状态来控制有机存储器件。

公开(公告)号：US20060139994A1

公开(公告)日：2006-06-29

申请号：US11021958

申请日：2004-12-23

申请人： Colin Bill ,  Swaroop Kaza ,  Tzu-Ning Fang ,  Stuart Spitzer

发明人： Colin Bill ,  Swaroop Kaza ,  Tzu-Ning Fang ,  Stuart Spitzer

IPC分类号： G11C11/36

CPC分类号： G11C11/36

摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.

摘要翻译： 存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。 在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。 在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。 每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。 通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

公开(公告)号：US20060104111A1

公开(公告)日：2006-05-18

申请号：US10990706

申请日：2004-11-17

申请人： Nicholas Tripsas ,  Colin Bill ,  Michael VanBuskirk ,  Matthew Buynoski ,  Tzu-Ning Fang ,  Wei Cai ,  Suzette Pangrle ,  Steven Avanzino

发明人： Nicholas Tripsas ,  Colin Bill ,  Michael VanBuskirk ,  Matthew Buynoski ,  Tzu-Ning Fang ,  Wei Cai ,  Suzette Pangrle ,  Steven Avanzino

IPC分类号： G11C11/36

CPC分类号： G11C13/003 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/56 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021

摘要： The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages

摘要翻译： 本存储器结构包括第一导体，第二导​​体，连接到第二导体的电阻性存储单元，连接到电阻存储单元和第一导体的第一二极管，并且从电阻存储单元向前取向 所述第一导体和连接到所述电阻性存储器单元和所述第一导体的第二二极管与所述第一二极管并联，并且在从所述电阻存储器单元到所述第一导体的相反方向上定向。 第一和第二二极管具有不同的阈值电压

公开(公告)号：US07916529B2

公开(公告)日：2011-03-29

申请号：US12370932

申请日：2009-02-13

申请人： Wai Lo ,  Christie Marrian ,  Tzu-Ning Fang ,  Sameer Haddad

发明人： Wai Lo ,  Christie Marrian ,  Tzu-Ning Fang ,  Sameer Haddad

IPC分类号： G11C11/36

CPC分类号： H01L27/1021 ,  G11C5/04 ,  G11C11/36 ,  H01L27/24 ,  H01L29/868

摘要： A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.

摘要翻译： 提供采用一个或多个半导体PIN二极管的存储架构。 存储器采用包括掩埋位/字线和PIN二极管的衬底。 PIN二极管包括非本征半导体区域，位/字线的一部分和位于非固有区域和位/字线部分之间的本征半导体区域。

公开(公告)号：US20100208517A1

公开(公告)日：2010-08-19

申请号：US12370932

申请日：2009-02-13

申请人： Wai Lo ,  Christie Marrian ,  Tzu-Ning Fang ,  Sameer Haddad

发明人： Wai Lo ,  Christie Marrian ,  Tzu-Ning Fang ,  Sameer Haddad

IPC分类号： G11C11/36 ,  H01L29/868 ,  H01L21/425 ,  G11C7/00

CPC分类号： H01L27/1021 ,  G11C5/04 ,  G11C11/36 ,  H01L27/24 ,  H01L29/868

摘要： A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.

摘要翻译： 提供采用一个或多个半导体PIN二极管的存储架构。 存储器采用包括掩埋位/字线和PIN二极管的衬底。 PIN二极管包括非本征半导体区域，位/字线的一部分和位于非固有区域和位/字线部分之间的本征半导体区域。

公开(公告)号：US07443710B2

公开(公告)日：2008-10-28

申请号：US10983919

申请日：2004-11-08

申请人： Tzu-Ning Fang ,  Michael Allen Van Buskirk ,  Colin S. Bill

发明人： Tzu-Ning Fang ,  Michael Allen Van Buskirk ,  Colin S. Bill

IPC分类号： G11C11/00

CPC分类号： G11C11/5664 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79

摘要： Systems and methods employing at least one constant current source to facilitate programming of an organic memory cell and/or employing at least one constant voltage source to facilitate erasing of a memory device. The present invention is utilized in single memory cell devices and memory cell arrays. Employing a constant current source prevents current spikes during programming and allows accurate control of a memory cell's state during write cycles, independent of the cell's resistance. Employing a constant voltage source provides a stable load for memory cells during erase cycles and allows for accurate voltage control across the memory cell despite large dynamic changes in cell resistance during the process.

摘要翻译： 采用至少一个恒定电流源的系统和方法促进有机存储器单元的编程和/或采用至少一个恒定电压源以便于擦除存储器件。 本发明用于单个存储器单元装置和存储单元阵列。 使用恒流源防止编程期间的电流尖峰，并允许在写周期期间精确控制存储单元的状态，而与电池的电阻无关。 使用恒定电压源在擦除周期期间为存储器单元提供稳定的负载，并且允许跨过存储器单元的精确的电压控制，尽管在该过程中电池电阻的大的动态变化。

公开(公告)号：US20080151669A1

公开(公告)日：2008-06-26

申请号：US11613832

申请日：2006-12-20

申请人： Colin S. Bill ,  Swaroop Kaza ,  Wei Daisy Cai ,  Tzu-Ning Fang ,  David Gaun ,  Eugen Gershon ,  Michael A. Van Buskirk ,  Jean Wu

发明人： Colin S. Bill ,  Swaroop Kaza ,  Wei Daisy Cai ,  Tzu-Ning Fang ,  David Gaun ,  Eugen Gershon ,  Michael A. Van Buskirk ,  Jean Wu

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431

摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.

摘要翻译： 公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法 跟踪元件的电阻已达到或超过预定参考阈值电阻值。 跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元 在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

公开(公告)号：US07379317B2

公开(公告)日：2008-05-27

申请号：US11021958

申请日：2004-12-23

申请人： Colin S. Bill ,  Swaroop Kaza ,  Tzu-Ning Fang ,  Stuart Spitzer

发明人： Colin S. Bill ,  Swaroop Kaza ,  Tzu-Ning Fang ,  Stuart Spitzer

IPC分类号： G11C5/06 ,  G11C17/06

CPC分类号： G11C11/36

摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.

摘要翻译： 存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。 在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。 在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。 每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。 通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

公开(公告)号：US07286388B1

公开(公告)日：2007-10-23

申请号：US11165005

申请日：2005-06-23

申请人： An Chen ,  Sameer Haddad ,  Tzu-Ning Fang ,  Yi-Ching Jean Wu ,  Colin S. Bill

发明人： An Chen ,  Sameer Haddad ,  Tzu-Ning Fang ,  Yi-Ching Jean Wu ,  Colin S. Bill

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/02 ,  G11C2013/009 ,  G11C2213/11 ,  G11C2213/56 ,  G11C2213/79

摘要： In the present method of programming a memory device from an erased state, the memory device includes first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrodes. In the programming method, (i) an electrical potential is applied across the first and second electrodes from higher to lower potential in one direction to reduce the resistance of the memory device, and (ii) an electrical potential is applied across the first and second electrodes from higher to lower potential in the other direction to further reduce the resistance of the memory device.

摘要翻译： 在从擦除状态编程存储器件的本方法中，存储器件包括第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层。 在编程方法中，（i）在一个方向上跨越第一和第二电极施加电位从较高电位到较低的电位，以减小存储器件的电阻，并且（ii）电势跨越第一和第二 电极在另一个方向从较高电位变为较低电位，以进一步降低存储器件的电阻。

公开(公告)号：US20070025166A1

公开(公告)日：2007-02-01

申请号：US11191126

申请日：2005-07-27

申请人： Tzu-Ning Fang ,  Colin Bill ,  Wei Cai ,  David Gaun ,  Eugen Gershon

发明人： Tzu-Ning Fang ,  Colin Bill ,  Wei Cai ,  David Gaun ,  Eugen Gershon

IPC分类号： G11C29/00

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0007 ,  G11C13/0016 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77

摘要： System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across the memory cell is detected and a lower input pulse is sent to the memory cell. Application of the lower pulse controls the data retention of the memory cell without disturbing the final programming state of the memory cell.

摘要翻译： 公开了改进和控制存储单元数据保持的系统和方法。 产生特定的脉冲宽度和幅度并将其施加到由至少两个电极制成的存储器单元，该至少两个电极在至少两个电极之间具有可控导电的介质。 检测存储器单元中的电流，并将较低的输入脉冲发送到存储单元。 下部脉冲的应用控制存储器单元的数据保持，而不会干扰存储单元的最终编程状态。