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    Method of aligning deposited nanotubes onto an etched feature using a spacer
    4.
    发明授权
    Method of aligning deposited nanotubes onto an etched feature using a spacer 有权
    使用间隔物将沉积的纳米管对准蚀刻特征的方法

    公开(公告)号：US07541216B2

    公开(公告)日：2009-06-02

    申请号：US11304871

    申请日：2005-12-14

    申请人： Colin D. Yates ,  Christopher L. Neville

    发明人： Colin D. Yates ,  Christopher L. Neville

    IPC分类号： H01L51/40

    CPC分类号： H01L21/76838 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

    摘要翻译： 公开了一种在纳米管层和凸起特征之间形成对准连接的方法。 具有凸起特征的基底具有靠近凸起特征侧面的间隔物。 蚀刻间隔物，直到突起特征的侧壁露出，在间隔物的顶部形成切口的特征。 形成图案化的纳米管层，使得纳米管层覆盖在间隔物的顶部并与凹口特征中的凸起特征的侧部接触。 然后用绝缘层覆盖纳米管层。 然后去除绝缘层的顶部以露出蚀刻特征的顶部。

    Reticle overlay correction
    5.
    发明授权
    Reticle overlay correction 有权
    标线重叠校正

    公开(公告)号：US07016041B2

    公开(公告)日：2006-03-21

    申请号：US10236226

    申请日：2002-09-06

    申请人： Colin D. Yates ,  James R. B. Elmer

    发明人： Colin D. Yates ,  James R. B. Elmer

    IPC分类号： G01B11/00

    CPC分类号： G03F7/70633

    摘要： A method for characterizing overlay errors between at least a first and a second mask layer for an integrated circuit. A first primary alignment structure is formed in a first position of the inter-layer region around the first mask layer, and a first secondary alignment structure is formed in a second position of the inter-layer region around the first mask layer. Similarly, a second primary alignment structure is formed in a first position of an inter-layer region around the second mask layer, and a second secondary alignment structure is formed in a second position of the inter-layer region around the second mask layer. The first mask layer and the second mask layer are exposed onto a photoresist coated substrate with a first exposure and a second exposure, where the first position of the first primary alignment structure during the first exposure generally aligns with the second position of the second secondary alignment structure, and the second position of the first secondary alignment structure during the second exposure generally aligns with the first position of the second primary alignment structure. The photoresist on the substrate is developed, and offsets between the first primary alignment structure and the second secondary alignment structure are measured, and offsets between the second primary alignment structure and the first secondary alignment structure are also measured, to determine the overlay errors.

    摘要翻译： 一种用于表征用于集成电路的至少第一和第二掩模层之间的覆盖误差的方法。 第一主对准结构形成在第一掩模层周围的层间区域的第一位置，第一次取向结构形成在第一掩模层周围的层间区域的第二位置。 类似地，第二主对准结构形成在第二掩模层周围的层间区域的第一位置，并且第二次取向结构形成在第二掩模层周围的层间区域的第二位置。 第一掩模层和第二掩模层在第一曝光和第二曝光下暴露在光致抗蚀剂涂覆的基板上，其中在第一曝光期间第一主对准结构的第一位置通常与第二次对准的第二位置对齐 并且在第二曝光期间第一次对准结构的第二位置通常与第二主对准结构的第一位置对准。 显影衬底上的光致抗蚀剂，并且测量第一主对准结构和第二次对准结构之间的偏移，并且还测量第二主对准结构和第一次对准结构之间的偏移，以确定重叠误差。

    System and method for performing optical proximity correction on the interface between optical proximity corrected cells
    6.
    发明授权
    System and method for performing optical proximity correction on the interface between optical proximity corrected cells 失效
    用于在光学邻近校正单元之间的接口上执行光学邻近校正的系统和方法

    公开(公告)号：US06425117B1

    公开(公告)日：2002-07-23

    申请号：US08937296

    申请日：1997-09-29

    申请人： Nicholas F. Pasch ,  Nicholas K. Eib ,  Colin D. Yates ,  Shumay Dou

    发明人： Nicholas F. Pasch ,  Nicholas K. Eib ,  Colin D. Yates ,  Shumay Dou

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068 ,  G03F1/36

    摘要： The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. A one-dimensional optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.

    摘要翻译： 该系统和方法通过在用于创建IC的单元格库上最初执行光学邻近校正来对集成电路（IC）掩模设计执行光学邻近校正。 预先测试的细胞被导入到面罩设计中。 所有细胞被放置在最小距离之间，以确保在完全集成在不同细胞中的元素之间不会发生邻近效应。 通过仅对在一个单元内未完全集成的那些组件（例如线）执行接近校正来对掩模设计执行一维光学邻近校正技术。

    Method of aligning nanotubes and wires with an etched feature
    7.
    发明授权
    Method of aligning nanotubes and wires with an etched feature 有权

    公开(公告)号：US08343373B2

    公开(公告)日：2013-01-01

    申请号：US12540869

    申请日：2009-08-13

    申请人： Colin D. Yates

    发明人： Colin D. Yates

    IPC分类号： C23F3/00

    CPC分类号： H01L21/76885 ,  B82Y10/00 ,  H01L21/76838 ,  H01L2221/1094 ,  Y10S977/742

    摘要： A method of forming an aligned connection between a nanotube layer and an etched feature is disclosed. An etched feature is formed having a top and a side and optionally a notched feature at the top. A patterned nanotube layer is formed such that the nanotube layer contacts portions of the side and overlaps a portion of the top of the etched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

    Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate
    8.
    发明授权
    Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate 失效
    使用半导体衬底上的集成电路结构的对准过程，使用在衬底上的间隔开的测试场中的潜像的散射测量

    公开(公告)号：US06809824B1

    公开(公告)日：2004-10-26

    申请号：US10006398

    申请日：2001-11-30

    申请人： Colin D. Yates ,  Nicholas F. Pasch ,  Nicholas K. Eib

    发明人： Colin D. Yates ,  Nicholas F. Pasch ,  Nicholas K. Eib

    IPC分类号： G01B1100

    CPC分类号： G03F7/70633 ,  G03F7/70675 ,  H01L22/34

    摘要： A process for measuring alignment of latent images in a photoresist layer of an integrated circuit structure on a semiconductor substrate with a test pattern formed in a lower layer on the substrate comprises the steps of forming a test pattern in selected fields of a first layer on a semiconductor substrate, forming a layer of photoresist over the first layer, forming latent images in portions of the photoresist layer lying in the selected fields overlying the test pattern of the first layer; and measuring the alignment of the test pattern in the selected fields of the first layer with the overlying latent images in the photoresist layer using scatterometry. In a preferred embodiment, the test pattern formed in each of the selected fields in the first layer comprises a pattern of parallel spaced apart lines, and the latent images formed in the portions of the photoresist layer in the selected fields above the test pattern in the first layer also comprises a pattern of parallel spaced part lines, with the two sets of lines interspaced between one another and generally parallel to one another to form a diffraction pattern.

    摘要翻译： 用于测量在半导体衬底上的集成电路结构的光致抗蚀剂层中的潜像与衬底上的下层中形成的测试图案的潜像的对准的方法包括以下步骤：在第一层的选定区域中形成测试图案 半导体衬底，在第一层上形成光致抗蚀剂层，在位于第一层的测试图案上的所选场域中的光致抗蚀剂层的部分中形成潜像; 并且使用散射测量在第一层的所选场域中的测试图案与光致抗蚀剂层中的上覆潜像的对准。 在优选实施例中，形成在第一层中的每个选定场中的测试图案包括平行间隔开的​​线的图案，并且在该测试图案上方的选定区域的光致抗蚀剂层的部分中形成的潜像 第一层还包括平行间隔的部分线的图案，其中两组线彼此间隔并且大体上彼此平行以形成衍射图案。