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公开(公告)号：US5315696A
公开(公告)日：1994-05-24
申请号：US748352
申请日：1991-08-21
申请人： Colyn Case , Kim Meinerth , John Irwin , Blaise Fanning
发明人： Colyn Case , Kim Meinerth , John Irwin , Blaise Fanning
摘要： In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. A separate translator provides conversion from generated virtual addresses to physical addresses. The address generator formulates addresses as a function of distance from the origin of desired destination area in destination memory to the requested position in the destination area. A plurality of drawing graphics commands specify different raster drawing operations. A plurality of context graphics commands is used to define a desired context in which drawing graphics commands operate. The defined context includes destination location for resulting data, type and plane depth of graphics operations, foreground and/or background color of resulting data. Different parts of the context are changeable/redefinable independently of the other parts.
摘要翻译： 在计算机图形系统中，地址生成器使用公共命令集处理物理和虚拟地址。 单独的翻译器提供从生成的虚拟地址到物理地址的转换。 地址生成器根据从目的地存储器中的期望目的地区域的原点到目的地区域中的请求位置的距离来形成地址。 多个绘图图形命令指定不同的光栅绘图操作。 使用多个上下文图形命令来定义绘图图形命令操作的所需上下文。 定义的上下文包括结果数据的目标位置，图形操作的类型和平面深度，结果数据的前景和/或背景颜色。 上下文的不同部分可以独立于其他部分进行变化/重新定义。
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公开(公告)号：US5321810A
公开(公告)日：1994-06-14
申请号：US748353
申请日：1991-08-21
申请人： Colyn Case , Kim Meinerth , John Irwin , Blaise Fanning
发明人： Colyn Case , Kim Meinerth , John Irwin , Blaise Fanning
CPC分类号： G09G5/363 , G09G5/14 , G09G5/39 , G09G2360/122 , G09G2360/127
摘要： In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. The address generator formulates addresses as a function of distance from the origin of the desired destination area in a destination memory to the requested position in the destination area. A plurality of context drawing commands is used to define a desired context in which drawing graphics commands operate. Different parts of the context are changeable/redefinable independently of the other parts. Graphics commands have a format of multiple fields having corresponding parameters arranged in order of common use of the parameter such that fields of less commonly used parameters are at an omittable end of the format. Raster drawing commands are delimited by a beginning and end indicator to form a drawing unit. For clip list processing, a drawing unit is stored as a single occurrence in the system command buffer.
摘要翻译： 在计算机图形系统中，地址生成器使用公共命令集处理物理和虚拟地址。 地址生成器根据从目的地存储器中的期望目的地区域的原点到目的地区域中的请求位置的距离的函数来形成地址。 使用多个上下文绘制命令来定义绘图图形命令操作的期望上下文。 上下文的不同部分可以独立于其他部分进行变化/重新定义。 图形命令具有多个字段的格式，其具有按照参数的共同使用顺序排列的相应参数，使得较不常用的参数的字段处于该格式的可忽略的结尾。 栅格绘图命令由开始和结束指示符分隔以形成绘图单元。 对于剪辑列表处理，在系统命令缓冲区中将绘制单元作为一次存储。
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3.发明授权Method and apparatus for varying command length in a computer graphics system 失效用于在计算机图形系统中改变命令长度的方法和装置
公开(公告)号：US5315698A
公开(公告)日：1994-05-24
申请号：US748354
申请日：1991-08-21
申请人： Colyn Case , Kim Meinerth , John Irwin , Blaise Fanning
发明人： Colyn Case , Kim Meinerth , John Irwin , Blaise Fanning
摘要： In a computer graphics system, an address generator processes physical and virtual addresses using a common command set. A separate translator provides conversion from generated virtual addresses to physical addresses. The address generator formulates addresses as a function of distance from the origin of desired destination area in destination memory to the requested position in the destination area. A plurality of drawing graphics commands specify different raster drawing operations. A plurality of context graphics commands is used to define a desired context in which drawing graphics commands operate. The defined context includes destination location for resulting data, type and plane depth of graphics operations, foreground and/or background color of resulting data. Different parts of the context are changeable/redefinable independently of the other parts. The graphics commands have a format of multiple fields. Different fields specify different parameters. For each graphics command, the fields are arranged in order of common use of the corresponding parameter such that fields of less commonly used parameters are at an omittable end of the format. Thus, length of each graphics command varies as a function of parameters specified in the graphics command. A desired set of raster drawing commands delimited by a beginning indicator and an end indicator form a drawing unit.
摘要翻译： 在计算机图形系统中，地址生成器使用公共命令集处理物理和虚拟地址。 单独的翻译器提供从生成的虚拟地址到物理地址的转换。 地址生成器根据从目的地存储器中的期望目的地区域的原点到目的地区域中的请求位置的距离来形成地址。 多个绘图图形命令指定不同的光栅绘图操作。 使用多个上下文图形命令来定义绘图图形命令操作的所需上下文。 定义的上下文包括结果数据的目标位置，图形操作的类型和平面深度，结果数据的前景和/或背景颜色。 上下文的不同部分可以独立于其他部分进行变化/重新定义。 图形命令具有多个字段的格式。 不同的字段指定不同的参数。 对于每个图形命令，这些字段按照相应参数的共同使用的顺序排列，使得较不常用的参数的字段处于格式的可忽略的结尾。 因此，每个图形命令的长度根据图形命令中指定的参数的函数而变化。 由开始指示符和结束指示符分隔的所需的一组光栅绘图命令形成绘图单元。
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公开(公告)号：US5313577A
公开(公告)日：1994-05-17
申请号：US748357
申请日：1991-08-21
申请人： Kim Meinerth , Colyn Case , Chris Franklin , Blaise Fanning , Rodney Gamache
发明人： Kim Meinerth , Colyn Case , Chris Franklin , Blaise Fanning , Rodney Gamache
CPC分类号： G09G5/39 , G06F12/1027 , G06F9/3879 , G09G5/06 , G09G5/08 , G06F12/0831 , G09G2360/121 , G09G2360/127
摘要： A computer graphics processor capable of reading from, and writing to, virtual memory. The invention provides a graphics processing unit which includes, among other things, an graphic processor in the form of an address generator which retrieves data from memory locations, and writes data to memory locations. The address generator retrieves data from memory locations memory access request directly to a memory control unit, which retrieves the contents of the memory location. Prior to issuing the request, the address generator sends the address to a virtual translation unit, which translates the virtual address to a physical address. The virtual translation/FIFO control unit also contains three translation buffers, in which are stored the most recently accessed virtual addresses, which, in many situations, enables the virtual translation/FIFO control unit to translate the virtual address using less memory accesses.
摘要翻译： 能够读取和写入虚拟内存的计算机图形处理器。 本发明提供了一种图形处理单元，其中包括地址发生器形式的图形处理器，其从存储器位置检索数据，并将数据写入存储单元。 地址生成器将存储器存储器访问请求中的数据直接检索到存储器控制单元，存储器控制单元检索存储器位置的内容。 在发出请求之前，地址生成器将地址发送到虚拟转换单元，该虚拟转换单元将虚拟地址转换为物理地址。 虚拟转换/ FIFO控制单元还包含三个转换缓冲器，其中存储最近访问的虚拟地址，在许多情况下，虚拟转换/ FIFO控制单元能够使用较少的存储器访问来转换虚拟地址。
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5.发明授权Method and apparatus for transmitting graphics command in a computer graphics system 失效用于在计算机图形系统中传输图形命令的方法和装置
公开(公告)号：US5321806A
公开(公告)日：1994-06-14
申请号：US748360
申请日：1991-08-21
申请人： Kim Meinerth , Colyn Case , Ali Moezzi , John Irwin , Agnes Masucci , Srinivasan Krishnaswami
发明人： Kim Meinerth , Colyn Case , Ali Moezzi , John Irwin , Agnes Masucci , Srinivasan Krishnaswami
CPC分类号： G09G5/363 , G06F9/3879 , G09G5/06 , G09G5/08 , G09G5/39 , G06F12/0831 , G09G2360/121 , G09G2360/127
摘要： A residue buffer, for temporary storage of portions of transmissions from a CPU to a graphics processor. Graphics commands are transmitted, in transmission units of uniform size, from a processor unit to an address generator, which processes the commands. The portion of the transmission unit not immediately usable by the graphics processor is stored in the residue buffer. The disclosure further describes a computer graphics system, having a graphics processor capable of reading from or writing to main memory, including virtual memory, without any action by the CPU; having a duplicate cache tag store accessible by the graphics system without generating traffic on the system bus; having a FIFO command buffer in main memory for temporary storage of graphics commands; having a "short circuit" feature for routing graphics commands to the command processor in the minimum number of steps; having a cursor control system capable of storing cursor pattern information in, and retrieving cursor pattern information from, main memory; having a cursor bus that is reconfigurable to carry information other than cursor information; and having a frame buffer module that contains no timing or cursor control circuitry.
摘要翻译： 一个残留缓冲器，用于临时存储从CPU到图形处理器的传输部分。 图形命令以统一大小的传输单元从处理器单元发送到处理命令的地址生成器。 不能由图形处理器立即使用的传输单元的部分被存储在剩余缓冲器中。 本公开进一步描述了一种计算机图形系统，其具有能够在没有CPU的任何动作的情况下能够从包括虚拟存储器的主存储器读取或写入的图形处理器; 具有由图形系统可访问的重复高速缓存标签存储器，而不在系统总线上产生流量; 在主存储器中具有用于临时存储图形命令的FIFO命令缓冲器; 具有用于以最小数量的步骤将图形命令路由到命令处理器的“短路”特征; 具有能够将光标图案信息存储在主存储器中并从主存储器检索光标图案信息的光标控制系统; 具有可重配置以携带除光标信息之外的信息的光标总线; 并具有不包含定时或光标控制电路的帧缓冲器模块。
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公开(公告)号：US6097402A
公开(公告)日：2000-08-01
申请号：US21192
申请日：1998-02-10
IPC分类号： G06F3/14 , G06F15/167
CPC分类号： G06F3/14
摘要： A method and system for enhancing graphics processing through selected placement of at least one graphics operand in main memory. The system includes a graphics controller in communication with system memory through a dedicated graphics bus such as an Accelerated Graphics Port (AGP) bus. This allows texture maps, alpha blending data and other graphics information to be contained in system memory without degradation of system performance.
摘要翻译： 一种用于通过在主存储器中选择放置至少一个图形操作数来增强图形处理的方法和系统。 该系统包括通过诸如加速图形端口（AGP）总线的专用图形总线与系统存储器通信的图形控制器。 这允许纹理贴图，alpha混合数据和其他图形信息包含在系统存储器中，而不会降低系统性能。
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7.发明授权Memory handling system that backfills dual-port buffer from overflow buffer when dual-port buffer is no longer full 失效当双端口缓冲区不再满时，内存处理系统从溢出缓冲区回填双端口缓冲区
公开(公告)号：US6044419A
公开(公告)日：2000-03-28
申请号：US941169
申请日：1997-09-30
申请人： George Hayek , Colyn Case
发明人： George Hayek , Colyn Case
CPC分类号： G06F5/06
摘要： The present invention relates to a method and apparatus for buffering data. The apparatus stores information in a buffer. When the buffer is full, overflow data is stored in an overflow memory. As data is removed from the buffer, the overflow data is transferred from overflow memory to the buffer.
摘要翻译： 本发明涉及一种用于缓冲数据的方法和装置。 该装置将信息存储在缓冲器中。 当缓冲区满时，溢出数据存储在溢出存储器中。 当数据从缓冲区中删除时，溢出数据从溢出存储器传输到缓冲区。
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8.发明授权High-throughput interconnect having pipelined and non-pipelined bus transaction modes 失效具有流水线和非流水线总线事务模式的高吞吐量互连公开(公告)号：US06317803B1
公开(公告)日：2001-11-13
申请号：US08721893
申请日：1996-09-27
申请人： Norman J. Rasmussen , Gary A. Solomon , David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case
发明人： Norman J. Rasmussen , Gary A. Solomon , David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case
IPC分类号： G06F1300
CPC分类号： G06F13/1615 , G06F13/161 , G06F13/1631
摘要： A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.
摘要翻译： 提供了高吞吐量的存储器访问端口。 该端口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。 该端口允许内存读取和写入请求流水线，以隐藏内存访问延迟的影响。 特别地，端口允许以非流水线模式（例如由PCI提供）或以流水线模式执行总线事务。 在流水线模式中，允许在第一存储器访问请求和其对应的数据传送之间插入一个或多个附加存储器访问请求。 相比之下，在非流水线模式下，不能在第一存储器访问请求和其对应的数据传输之间插入附加存储器访问请求。
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公开(公告)号：US20070079044A1
公开(公告)日：2007-04-05
申请号：US11538399
申请日：2006-10-03
申请人： Manas Mandal , William Tsu , Colyn Case , Ashish Kaul
发明人： Manas Mandal , William Tsu , Colyn Case , Ashish Kaul
IPC分类号： G06F13/36
CPC分类号： G06F13/404 , Y02D10/14 , Y02D10/151
摘要： Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportunistic merging procedure is advantageously used that merges a first request with a later request if the first request and the later request are mergeable and are received within a holdoff period that is dynamically determined based on a level of bus activity; otherwise, requests can be transmitted without merging.
摘要翻译： 多个数据传输请求可以在诸如PCI Express（PCI-E）总线的分组化总线上合并并发送为单个数据包。 在一个实施例中，如果它们被引导到相同目标设备中的连续地址范围，则组合请求。 有利地使用机会主义合并过程，如果第一请求和后期请求可合并并且在基于总线活动级别动态确定的保留期间内被接收，则将第一请求与稍后的请求合并; 否则，可以在不合并的情况下传送请求。
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10.发明授权High-throughput interconnect allowing bus transactions based on partial access requests 失效高吞吐量互连允许基于部分访问请求的总线事务
公开(公告)号：US5911051A
公开(公告)日：1999-06-08
申请号：US721686
申请日：1996-09-27
申请人： David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case , Kim A. Meinerth , Brian K. Langendorf
发明人： David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case , Kim A. Meinerth , Brian K. Langendorf
CPC分类号： G06F13/1631 , G06F13/161 , G06F13/1615
摘要： A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target. If such segment or segments have changed since the previous access request, then they are provided to the target only for purposes of updating state in the target. Access requests may optionally be provided to the target on a separate port from the port used to transmit data in response to access requests.
摘要翻译： 提供了高吞吐量的存储器访问接口。 该接口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。 该接口允许以这样的方式执行存储器访问请求，使得只有访问请求的一部分需要被发送到目标设备以用于某些总线事务。 每个访问请求包括命令位，地址位和长度位。 在发起设备中，每个访问请求被分成三个段，它们存储在起始设备和目标设备中的单独的寄存器中。 目标设备只需要包含最低位地址位和长度位的段来启动总线事务。 因此，如果其他两个段中的任何一个从先前的访问请求起没有改变，则这样的段或段不被发送到目标。 如果这些片段或片段自从先前的访问请求以来已经改变，那么它们被提供给目标，仅用于更新目标中的状态。 访问请求可以可选地在与用于响应于访问请求传输数据的端口的单独端口上提供给目标。
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