-
公开(公告)号:US20170179954A1
公开(公告)日:2017-06-22
申请号:US15381477
申请日:2016-12-16
发明人: Hervé Fanet , Samer Houri , Gaël Pillonnet
IPC分类号: H03K19/00 , H03K19/185
CPC分类号: H03K19/0008 , H03K19/0013 , H03K19/0019 , H03K19/02 , H03K19/185 , H03K19/20
摘要: The invention relates to a logic cell for an integrated circuit including at least one first variable-capacitance capacitor having first and second main electrodes separated by an insulating region, and a third control electrode capable of receiving a control voltage referenced to a reference node of the cell to vary the capacitance between the first and second main electrodes, the third electrode being coupled to a node of application of a first logic input signal of the cell, and the first and second electrodes being respectively coupled to a node of application of a cell power supply voltage and to a node for supplying a logic output signal of the cell.
-
公开(公告)号:US10916379B2
公开(公告)日:2021-02-09
申请号:US16006576
申请日:2018-06-12
发明人: Gaël Pillonnet , Philippe Basset , Hervé Fanet , Hatem Samaali
摘要: A variable-capacitance capacitor having first and second electrodes mobile with respect to each other and third and fourth electrodes insulated from the first and second electrodes, capable of receiving a control signal to vary the relative position of the first and second electrodes in order to vary the capacitance between the first and second electrodes, the capacitor further including a system for controlling the position of the second electrode with respect to the first electrode, the system being arranged so that, for at least one relative position of the second electrode with respect to the first electrode, the position of the second electrode with respect to the first electrode is independent from the voltage between the first and second electrodes.
-
公开(公告)号:US09979393B2
公开(公告)日:2018-05-22
申请号:US15381477
申请日:2016-12-16
发明人: Hervé Fanet , Samer Houri , Gaël Pillonnet
IPC分类号: H03K19/00 , H03K19/185 , H03K19/02
CPC分类号: H03K19/0008 , H03K19/0013 , H03K19/0019 , H03K19/02 , H03K19/185 , H03K19/20
摘要: The invention relates to a logic cell for an integrated circuit including at least one first variable-capacitance capacitor having first and second main electrodes separated by an insulating region, and a third control electrode capable of receiving a control voltage referenced to a reference node of the cell to vary the capacitance between the first and second main electrodes, the third electrode being coupled to a node of application of a first logic input signal of the cell, and the first and second electrodes being respectively coupled to a node of application of a cell power supply voltage and to a node for supplying a logic output signal of the cell.
-
公开(公告)号:US20200153436A1
公开(公告)日:2020-05-14
申请号:US16673718
申请日:2019-11-04
发明人: Hervé Fanet , Gaël Pillonnet
IPC分类号: H03K19/09 , H03K19/0944
摘要: A logic cell, including a first capacitor connected between an application node for applying a supply voltage of the cell and a floating node for providing an output logic signal of the cell, and, connected in parallel with the first capacitor, an association in series of a second capacitor and a first variable-resistance element, the first variable-resistance element including a control electrode connected to an application node for applying a first input logic signal of the cell.
-
公开(公告)号:US10593485B2
公开(公告)日:2020-03-17
申请号:US16044126
申请日:2018-07-24
发明人: Gaël Pillonnet , Yann Perrin , Ayrat Galisultanov , Hervé Fanet
IPC分类号: H01G5/16 , H03K19/00 , H03K19/185 , H03K19/20 , H03K19/02 , H01L23/64 , H01L23/00 , H01L23/495 , H03K4/94 , H01L23/66
摘要: A logic cell including a fixed assembly including a first electrode, a mobile assembly including a second electrode, and third, fourth, and fifth electrodes, wherein: the first, second, third, fourth, and fifth electrodes are insulated from one another; the first and second electrodes define a capacitor variable according to the position of the mobile assembly relative to the fixed assembly; the third electrode is connected to a node of application of a first logic input signal; the fourth electrode is connected to a node of application of a second logic input signal; the fifth electrode is connected to a reference node; and the position of the second electrode relative to the first electrode is a function of a combination of the first and second logic input signals.
-
公开(公告)号:US20190043671A1
公开(公告)日:2019-02-07
申请号:US16053521
申请日:2018-08-02
发明人: Ayrat Galisultanov , Hervé Fanet , Yann Perrin , Gaël Pillonnet
IPC分类号: H01G5/16 , H03K3/0231 , H01G5/013 , H01G5/011
摘要: A system including first and second electric or electronic circuits galvanically isolated from each other, and a coupling device coupling the first circuit to the second circuit, the coupling device including a variable-capacitance capacitor including first and second electrodes mobile with respect to each other, separated by an insulating region, and third and fourth electrodes electrically insulated from the first and second electrodes, capable of receiving a control signal to vary, by an electrostatic, electromagnetic, or piezoelectric actuation mechanism, the relative position of the first and second electrodes, to vary the capacitance between the first and second electrodes.
-
公开(公告)号:US10964373B2
公开(公告)日:2021-03-30
申请号:US16567927
申请日:2019-09-11
发明人: Yann Perrin , Hervé Fanet , Ayrat Galisultanov , Gaël Pillonnet
摘要: A memory cell in capacitive logic, including a bistable system including a fixed element and a mobile element capable of taking one or the other of two stable positions with respect to the fixed element; a read device including a variable-capacitance capacitor including a first fixed electrode and a second mobile electrode rigidly fixed to the mobile element; and an electrically controllable write device for placing the mobile element in one or the other of its two stable positions.
-
公开(公告)号:US10720924B2
公开(公告)日:2020-07-21
申请号:US16673677
申请日:2019-11-04
发明人: Gaël Pillonnet , Hervé Fanet
IPC分类号: H03K19/00 , H03K19/094 , H03K19/0185
摘要: An adiabatic logic cell including a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first transistor is a dual-gate transistor including a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage.
-
公开(公告)号:US20200082867A1
公开(公告)日:2020-03-12
申请号:US16567927
申请日:2019-09-11
发明人: Yann Perrin , Hervé Fanet , Ayrat Galisultanov , Gaël Pillonnet
摘要: A memory cell in capacitive logic, including a bistable system including a fixed element and a mobile element capable of taking one or the other of two stable positions with respect to the fixed element; a read device including a variable-capacitance capacitor including a first fixed electrode and a second mobile electrode rigidly fixed to the mobile element; and an electrically controllable write device for placing the mobile element in one or the other of its two stable positions.
-
公开(公告)号:US20180366272A1
公开(公告)日:2018-12-20
申请号:US16006576
申请日:2018-06-12
发明人: Gaël Pillonnet , Philippe Basset , Hervé Fanet , Hatem Samaali
摘要: A variable-capacitance capacitor having first and second electrodes mobile with respect to each other and third and fourth electrodes insulated from the first and second electrodes, capable of receiving a control signal to vary the relative position of the first and second electrodes in order to vary the capacitance between the first and second electrodes, the capacitor further including a system for controlling the position of the second electrode with respect to the first electrode, the system being arranged so that, for at least one relative position of the second electrode with respect to the first electrode, the position of the second electrode with respect to the first electrode is independent from the voltage between the first and second electrodes.
-
-
-
-
-
-
-
-
-