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公开(公告)号:US11688811B2
公开(公告)日:2023-06-27
申请号:US17123231
申请日:2020-12-16
IPC分类号: H01L29/786 , H01L29/78 , H01L29/10 , H01L29/423 , H01L29/49 , H01L29/66 , H01L27/12
CPC分类号: H01L29/78696 , H01L27/127 , H01L27/1222 , H01L29/1033 , H01L29/1037 , H01L29/42384 , H01L29/4908 , H01L29/66545 , H01L29/66742 , H01L29/66772 , H01L29/78 , H01L29/7842 , H01L29/78654
摘要: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.
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公开(公告)号:US11469137B2
公开(公告)日:2022-10-11
申请号:US17124184
申请日:2020-12-16
发明人: Shay Reboh , Pablo Acosta Alba , Emmanuel Augendre
IPC分类号: H01L21/762 , H01L21/763 , H01L23/66 , H01L27/12
摘要: A method for manufacturing a semiconductor-on-insulator type substrate for radiofrequency applications is provided, including the steps of: directly bonding a support substrate of a single crystal material and a donor substrate including a thin layer of a semiconductor material, one or more layers of dielectric material being at a bonding interface thereof; transferring the thin layer onto the support substrate; and forming an electric charge trap region in the support substrate in contact with the one or more layers of the dielectric material present at the bonding interface, by transforming a buried zone of the support substrate into a polycrystal.
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公开(公告)号:US10714392B2
公开(公告)日:2020-07-14
申请号:US16038985
申请日:2018-07-18
申请人: International Business Machines Corporation , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人: Nicolas Loubet , Emmanuel Augendre , Remi Coquand , Shay Reboh
IPC分类号: H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/06 , H01L29/78 , H01L29/423 , H01L27/088 , H01L21/3065 , H01L21/306
摘要: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.
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公开(公告)号:US10600786B2
公开(公告)日:2020-03-24
申请号:US15452049
申请日:2017-03-07
IPC分类号: H01L27/092 , H01L21/02 , H01L21/266 , H01L21/268 , H01L21/8238 , H01L29/10 , H01L29/66
摘要: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.
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公开(公告)号:US20200027791A1
公开(公告)日:2020-01-23
申请号:US16038985
申请日:2018-07-18
申请人: International Business Machines Corporation , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人: Nicolas Loubet , Emmanuel Augendre , Remi Coquand , Shay Reboh
IPC分类号: H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/06 , H01L29/78 , H01L29/423 , H01L27/088
摘要: Techniques for optimizing junctions of a gate-all-around nanosheet device are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of first/second nanosheets including a first/second material as a stack on a wafer; forming a dummy gate(s) on the stack; patterning the stack into a fin stack(s) beneath the dummy gate(s); etching the fin stack(s) to selectively pull back the second nanosheets in the fin stack(s) forming pockets in the fin stack(s); filling the pockets with a strain-inducing material; burying the dummy gate(s) in a dielectric material; selectively removing the dummy gate(s) forming a gate trench(es) in the dielectric material; selectively removing either the first nanosheets or the second nanosheets from the fin stack(s); and forming a replacement gate(s) in the gate trench(es). A nanosheet device is also provided.
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公开(公告)号:US10269930B2
公开(公告)日:2019-04-23
申请号:US15837217
申请日:2017-12-11
发明人: Shay Reboh , Emmanuel Augendre , Remi Coquand
IPC分类号: H01L21/00 , H01L29/66 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/786 , H01L29/161
摘要: Method for producing a semiconductor device, comprising: producing a stack including a first crystalline semiconductor portion intended to form a channel and arranged on at least one second portion which can be selectively etched vis-à-vis the first portion, producing a dummy gate and external spacers, etching the stack, a remaining part of the stack under the dummy gate and the external spacers being conserved, producing source/drain by epitaxy from the remaining part of the stack; removing the dummy gate and the second portion, oxidizing portions of the source/drain from the parts of the source/drain revealed by the removal of the second portion, forming internal spacers, producing a gate electrically insulated from the source/drain by the external and internal spacers.
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7.
公开(公告)号:US10217849B2
公开(公告)日:2019-02-26
申请号:US15837298
申请日:2017-12-11
发明人: Sylvain Barraud , Emmanuel Augendre , Remi Coquand , Shay Reboh
IPC分类号: H01L21/00 , H01L29/66 , H01L29/06 , H01L29/423 , H01L29/78 , H01L29/786
摘要: Method for making a semiconductor device, comprising: a) making of a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being selectively etched in relation to the first layer, b) etching of part of the stack, a portion of the first layer forms a nanowire (132) arranged on the second layer, c) selective etching of second layer, d) making, beneath the nanowire, of a sacrificial portion which has an etching selectivity which is greater than that of the second layer, e) making of a sacrificial gate and of an external spacer surrounding the sacrificial gate, f) etching of the stack, revealing ends of the nanowire and of the sacrificial portion aligned with the external spacer, g) selective etching of parts of the sacrificial portion, from its ends, forming aligned cavities beneath the external spacer, h) making of an internal spacer within the cavities.
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8.
公开(公告)号:US20170263607A1
公开(公告)日:2017-09-14
申请号:US15452049
申请日:2017-03-07
IPC分类号: H01L27/092 , H01L21/266 , H01L21/8238 , H01L21/268 , H01L21/02 , H01L27/12 , H01L29/10 , H01L29/66
摘要: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphisation recrystallisation then germanium condensation.
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公开(公告)号:US10256102B2
公开(公告)日:2019-04-09
申请号:US15938321
申请日:2018-03-28
发明人: Remi Coquand , Emmanuel Augendre , Shay Reboh
IPC分类号: H01L21/285 , H01L29/66 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/775 , H01L29/06 , H01L29/08 , H01L21/02 , H01L29/45 , H01L29/786
摘要: A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.
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10.
公开(公告)号:US09997394B2
公开(公告)日:2018-06-12
申请号:US14901027
申请日:2014-06-27
IPC分类号: H01L21/30 , H01L21/46 , H01L21/762 , H01L21/428 , H01L23/00
CPC分类号: H01L21/76254 , H01L21/428 , H01L24/83 , H01L2224/29147 , H01L2224/83895
摘要: A method of transferring a thin layer from a first substrate to a second substrate with different coefficients of thermal expansion, including: providing at least one intermediate layer which temperature is increased by induction when an electromagnetic field is applied to it, more than a temperature increase in the first and second substrates; making contact between the first substrate and the second substrate, with the at least one intermediate layer interposed between them; fracturing the first substrate at a weakened zone making use of supply of thermal energy at the weakened zone made by applying an electromagnetic field to a heterostructure formed by making contact between the first substrate and the second substrate, the application generating local induction heating in the intermediate layer that induces a temperature gradient with a local value at the weakened zone activating the fracture mechanism.
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