公开(公告)号：US6105083A

公开(公告)日：2000-08-15

申请号：US879981

申请日：1997-06-20

申请人： Jeffrey D. Kurtze ,  Craig R. Frink ,  James Hamilton ,  Frank C. Sarnowski ,  Raymond D. Cacciatore ,  Scott A. Markinson ,  Michael F. Lamenza ,  Anthony O'Connor ,  Hamed Eshraghian

发明人： Jeffrey D. Kurtze ,  Craig R. Frink ,  James Hamilton ,  Frank C. Sarnowski ,  Raymond D. Cacciatore ,  Scott A. Markinson ,  Michael F. Lamenza ,  Anthony O'Connor ,  Hamed Eshraghian

IPC分类号： G06F13/38 ,  G06F13/42 ,  H04N7/24 ,  H04N7/26 ,  H04N7/50

CPC分类号： G06F13/4213 ,  H04N19/42 ,  H04N19/61 ,  H04N7/24

摘要： The present invention provides a generic interface which enables asynchronous data processing elements to be interconnected using an interconnection protocol that controls flow of data between the processing elements. The flow control allows the processing elements to be data independent from, i.e., the processing elements need not be designed for a fixed sample rate or resolution, sample format and other data dependent factors. When used with digital motion video data, the processing elements may process motion video data at various temporal and spatial resolutions and color formats. Flow of data between processing elements may be controlled by handshake signals indicating whether the sender has valid data and the receiver can receive data. When valid data is available at the sender and is requested by the receiver, a transfer of data occurs. The characteristics of the data, and functions to be performed on the data may be specified using control inputs to the processing elements. A counting circuit may be used to specify the number of the data samples for which the control inputs are valid. The interface allows each processing element to have a small number of storage locations for storing data, such as a pair of registers, which eliminates the need for large buffers and simplifies implementation of the processing element with such flow control as a simple integrated circuit.

摘要翻译： 本发明提供了一种通用接口，其使得能够使用控制处理元件之间的数据流的互连协议来互连异步数据处理元件。 流量控制允许处理元件与数据无关，即处理元件不需要被设计用于固定的采样率或分辨率，采样格式和其他依赖于数据的因素。 当与数字运动视频数据一起使用时，处理元件可以处理各种时间和空间分辨率和颜色格式的运动视频数据。 处理元件之间的数据流可以由指示发送者是否具有有效数据并且接收方可以接收数据的握手信号来控制。 当有效数据在发送器处可用并且被接收器请求时，发生数据传送。 可以使用对处理元件的控制输入来指定数据的特性和对数据执行的功能。 可以使用计数电路来指定控制输入有效的数据样本的数量。 该接口允许每个处理元件具有用于存储数据的少量存储位置，诸如一对寄存器，其消除了对大缓冲器的需要并且简化了具有如简单集成电路的流量控制的处理元件的实现。

公开(公告)号：US09031079B1

公开(公告)日：2015-05-12

申请号：US10912041

申请日：2004-08-06

申请人： Craig R. Frink

发明人： Craig R. Frink

IPC分类号： H04L12/28 ,  H04L12/26

CPC分类号： H04L47/22 ,  H04J3/247 ,  H04L12/5601 ,  H04L43/062 ,  H04L47/50 ,  H04L47/568 ,  H04L47/6205 ,  H04L49/254 ,  H04L49/3081 ,  H04L49/9005 ,  H04L2012/568

摘要： Stacked (i.e., hierarchically arranged) rate wheels schedule traffic flows in a network. A first rate wheel operates to efficiently schedule traffic flows in which traffic shaping parameters may be applied to individual traffic flows. A second rate wheel schedules group of the traffic flows in which traffic shaping parameters may be applied at the group level. In the context of an ATM network, the first rate wheel may operate at the virtual circuit level and the second rate wheel may operate at the virtual path level.

摘要翻译： 堆叠（即，分层布置）速率轮调度网络中的业务流。 第一速率轮操作以有效地调度可以将流量整形参数应用于个体业务流的业务流。 第二速率轮调度可以在组级别应用流量整形参数的业务流的组。 在ATM网络的上下文中，第一速率轮可以在虚拟电路级操作，并且第二速率轮可以在虚拟路径级别操作。

公开(公告)号：US07583596B1

公开(公告)日：2009-09-01

申请号：US10876624

申请日：2004-06-28

申请人： Craig R. Frink

发明人： Craig R. Frink

IPC分类号： H04J3/14 ,  H04L12/28 ,  H04L12/54

CPC分类号： H04L12/5601 ,  H04L47/50 ,  H04L47/568 ,  H04L47/6215 ,  H04L49/205 ,  H04L49/30 ,  H04L2012/5652 ,  H04L2012/5679

摘要： A system schedules traffic flows on an output port using circular memory structures. The circular memory structures may include rate wheels that include a group of sequentially arranged slots. The traffic flows may be assigned to different rate wheels on a per-priority basis.

摘要翻译： 系统使用循环存储器结构在输出端口上调度流量。 圆形存储器结构可以包括包括一组顺序布置的槽的速率轮。 交通流量可以按优先级分配给不同的速率轮。

公开(公告)号：US07457247B1

公开(公告)日：2008-11-25

申请号：US10876625

申请日：2004-06-28

申请人： Craig R. Frink

发明人： Craig R. Frink

IPC分类号： G06F11/00 ,  G06F15/16

CPC分类号： H04L47/6205 ,  H04L12/5601 ,  H04L47/50 ,  H04L47/568 ,  H04L49/3081 ,  H04L2012/5652 ,  H04L2012/5679 ,  H04L2012/5681

摘要： A system schedules traffic flows on an output port using a circular memory structure. The circular memory structure may be a rate wheel that includes a group of sequentially arranged slots. The rate wheel schedules the traffic flows in select ones of the slots based on traffic shaping parameters assigned to the flows. The rate wheel compensates for collisions between multiple flows that occur in the slots by subsequently skipping empty slots.

摘要翻译： 系统使用循环存储器结构在输出端口上调度流量。 循环存储器结构可以是包括一组顺序排列的槽的速率轮。 速率轮根据分配给流量的流量整形参数来调度某些时隙中的流量。 速率轮通过随后跳过空槽来补偿在槽中发生的多个流之间的冲突。

公开(公告)号：US06678002B2

公开(公告)日：2004-01-13

申请号：US09800883

申请日：2001-03-07

申请人： Craig R. Frink ,  Raymond Cacciatoro

发明人： Craig R. Frink ,  Raymond Cacciatoro

IPC分类号： H04N701

CPC分类号： H04N5/262 ,  G11B27/034 ,  G11B2220/415

摘要： A system provides real-time previsualization of effects to be added to high definition (HD) video data and real-time rendering of the HD video data including the added effects. The computer based system for editing high definition television (HDTV) resolution video includes a high definition video system connected to a standard definition video system and a high definition storage system. A resizer reformats the high definition video data to standard definition resolution for real-time processing and previsualization.

摘要翻译： 系统提供对要添加到高分辨率（HD）视频数据的效果的实时预先查看，以及包括添加的效果的HD视频数据的实时渲染。 用于编辑高分辨率电视（HDTV）分辨率视频的基于计算机的系统包括连接到标准清晰度视频系统和高清晰度存储系统的高清晰度视频系统。 调整器将高分辨率视频数据重新格式化为标准清晰度分辨率，用于实时处理和预视。

公开(公告)号：US07046251B2

公开(公告)日：2006-05-16

申请号：US10375599

申请日：2003-02-27

申请人： Morton Tarr ,  Peter Fasciano ,  Craig R. Frink

发明人： Morton Tarr ,  Peter Fasciano ,  Craig R. Frink

IPC分类号： H04N5/14

CPC分类号： G11B27/034 ,  H04N5/262

摘要： A non-linear editor is connected to video processing equipment through a serial digital video interface to edit high definition (HD) television video data. The non-linear editor includes a randomly accessible, computer-readable and re-writeable storage medium that stores a plurality of sequences of HD digital images representing a frame or field of HD motion video data. The non-linear editor provides a configuration control signal to identify processing to be performed on the HD video data and defines a video program to be rendered using the stored HD digital images. An input serial digital interface and an output serial digital interface in the non-linear editor provide the HD video data to be edited. A multiformat video router controls the HD video data sent between the non-linear editor and the video processing equipment. The router is video interconnected to the video processing equipment and to the serial digital interfaces of the non-linear editor.

公开(公告)号：US06961801B1

公开(公告)日：2005-11-01

申请号：US09054933

申请日：1998-04-03

申请人： Craig R. Frink

发明人： Craig R. Frink

IPC分类号： H04N21/643 ,  G06F13/36

CPC分类号： H04N21/643

摘要： Command data may be embedded in the data transmitted over an interconnect between video devices to specify memory addresses in a destination device. Using an embedded address allows address-dependent data to be transmitted over the interconnect without losing these attributes. For example, compressed video may be transferred from a disk controller to a memory device using this interconnection protocol without losing address attributes of the bus architecture. The address information may be used either to read data from or to write data to a device over the interconnect into randomly-accessible memory locations.

摘要翻译： 命令数据可以嵌入在通过视频设备之间的互连传输的数据中，以指定目的地设备中的存储器地址。 使用嵌入式地址可以通过互连传输与地址相关的数据，而不会丢失这些属性。 例如，压缩视频可以使用这种互连协议从磁盘控制器传送到存储设备，而不会丢失总线架构的地址属性。 地址信息可用于通过互连将数据从数据读取或写入设备到随机可访问的存储器位置。

公开(公告)号：US06182176B2

公开(公告)日：2001-01-30

申请号：US08201185

申请日：1994-02-24

申请人： Michael L. Ziegler ,  Robert J. Brooks ,  William R. Bryg ,  Craig R. Frink ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  John L. Wood

发明人： Michael L. Ziegler ,  Robert J. Brooks ,  William R. Bryg ,  Craig R. Frink ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  John L. Wood

IPC分类号： G06F1314

CPC分类号： G06F13/36

摘要： A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.

摘要翻译： 共享总线系统，其具有总线和耦合到总线的一组客户端模块。 每个客户端模块都能够将总线上的事务发送到其他客户端模块，并从其他客户端模块接收总线上的事务处理。 每个模块都有一个队列，用于存储由模块接收的事务处理。 总线控制器限制可以在总线上发送的事务的类型，以防止任何模块的队列溢出。

公开(公告)号：US06407775B1

公开(公告)日：2002-06-18

申请号：US09293332

申请日：1999-04-16

申请人： Craig R. Frink ,  Raymond D. Cacciatore

发明人： Craig R. Frink ,  Raymond D. Cacciatore

IPC分类号： H04N701

CPC分类号： H04N7/01 ,  H04N5/14 ,  H04N7/0112

摘要： Film frames, or other images in which fields are captured at the same point in time, may be processed as a sequence of temporally coherent image fields or as progressive images. Such images may be obtained, for example, by digitizing signals from a telecine and dropping redundant fields inserted by the telecine. These fields may be stored in a buffer. Two fields of a given frame are read from the buffer by a resizer in accordance with read instructions, which may be determined according to any specified pulldown sequence, an output image size, and resize instructions, such as pan and scan or letterbox instructions. The resizer also may be informed of the input image size if it is not presumed. Thus, the full input image from which an output image may be generated is used by the resizer to generate output image. The resizer uses data in the input image received at one rate to generate one output image at the output rate. The resize instructions, if varied over time, are determined for each output image at the output image rate. For example, if a pan and scan operation is specified to move from a first position to a second position over two input images, the position of the sampled area may be determined by interpolating between the first and second positions and sampling along the interpolated curve for each output image. Thus, the sampled area of the input image is different for each output field. Because changes in position of the sampled area are made in increments at the temporal resolution and ordering of the output images, artifacts in the output images are reduced.

摘要翻译： 在相同时间点捕获场的胶片帧或其他图像可以被处理为时间相干图像场序列或逐行图像。 这样的图像可以例如通过数字化来自电视电影的信号和丢弃由电视电影机插入的冗余字段来获得。 这些字段可以存储在缓冲区中。 根据读取的指令，通过调整器从缓冲器读取给定帧的两个字段，读取指令可以根据任何指定的下拉顺序，输出图像大小和调整大小的指令（诸如平移和扫描或信箱指令）来确定。 如果不推测，调整器也可以被通知输入图像大小。 因此，可以由生成输出图像的整个输入图像被生成输出图像。 调整器使用以一个速率接收的输入图像中的数据以输出速率生成一个输出图像。 如果随时间变化，则按照输出图像速率为每个输出图像确定调整大小的指令。 例如，如果指定了平移和扫描操作以在两个输入图像上从第一位置移动到第二位置，则可以通过在第一和第二位置之间进行插值并沿着内插曲线进行采样来确定采样区域的位置 每个输出图像。 因此，输入图像的采样区域对于每个输出场是不同的。 由于采样区域的位置变化是以输出图像的时间分辨率和顺序增量进行的，输出图像中的伪影减少。

公开(公告)号：US06229576B1

公开(公告)日：2001-05-08

申请号：US09055048

申请日：1998-04-03

申请人： Morton Tarr ,  Peter Fasciano ,  Craig R. Frink

发明人： Morton Tarr ,  Peter Fasciano ,  Craig R. Frink

IPC分类号： H04N514

CPC分类号： G11B27/034 ,  G11B27/032 ,  G11B2220/90 ,  H04N5/262

摘要： A non-linear editor is connected to video processing equipment through a serial digital video interface to edit high definition (HD) television video data. The non-linear editor includes a randomly accessible, computer-readable and re-writeable storage medium that stores a plurality of sequences of HD digital images representing a frame or field of HD motion video data. The non-linear editor provides a configuration control signal to identify processing to be performed on the HD video data and defines a video program to be rendered using the stored HD digital images. An input serial digital interface and an output serial digital interface in the non-linear editor provide the HD video data to be edited. A multiformat video router controls the HD video data sent between the non-linear editor and the video processing equipment. The router is video interconnected to the video processing equipment and to the serial digital interfaces of the non-linear editor.