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1.发明申请System and Method for Achieving Cache Coherency Within Multiprocessor Computer System 审中-公开在多处理器计算机系统中实现缓存一致性的系统和方法公开(公告)号：US20080270708A1
公开(公告)日：2008-10-30
申请号：US11741858
申请日：2007-04-30
申请人： Craig Warner , Bryan Hornung , Chris Michael Brueggen , Ryan L. Akkerman , Michael K. Dugan , Gary Gostin , Harvey Ray , Dan Robinson , Christopher Greer
发明人： Craig Warner , Bryan Hornung , Chris Michael Brueggen , Ryan L. Akkerman , Michael K. Dugan , Gary Gostin , Harvey Ray , Dan Robinson , Christopher Greer
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0831 , G06F2212/1048
摘要： A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled. In at least some embodiments, the caching devices track remote cache line ownership for processor and/or input/output hub caches.
摘要翻译： 公开了一种用于在具有多个具有处理设备和存储器控制器以及多个存储器块的套接字的多处理器计算机系统中实现高速缓存一致性的系统和方法。 在至少一些实施例中，系统包括能够分别耦合到多处理器计算机的相应插槽的多个节点控制器，分别耦合到相应节点控制器的多个高速缓存设备，以及耦合各个节点控制器的结构， 由此可以在相应的节点控制器之间传送高速缓存行请求信号。 尽管至少部分地由于节点控制器与节点控制器所耦合的相应的高速缓存设备之间的通信而在各个节点控制器之间传送高速缓存行请求信号，仍然实现了高速缓存一致性。 在至少一些实施例中，缓存设备跟踪用于处理器和/或输入/输出集线器高速缓存的远程高速缓存行所有权。
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公开(公告)号：US20060023819A1
公开(公告)日：2006-02-02
申请号：US10901762
申请日：2004-07-29
申请人： Richard Adkisson , Gary Gostin , Christopher Greer
发明人： Richard Adkisson , Gary Gostin , Christopher Greer
IPC分类号： H04L7/00
CPC分类号： H04L7/0012
摘要： A clock synchronizer for effectuating data transfer between first and second clock domains by utilizing first and second synchronizer controllers. The first synchronizer controller circuit operates in the first clock domain which has N first clock cycles and the second synchronizer controller circuit operates in the second clock domain which has M second clock cycles, wherein N/M≧1. Inversion circuitry inverts a first clock signal associated with the first clock domain to generate an inverted first clock signal which is used in effectuating a SYNC pulse during coincident edges of the inverted first clock signal and a second clock signal associated with the second clock domain.
摘要翻译： 一种时钟同步器，用于通过利用第一和第二同步器控制器来实现第一和第二时钟域之间的数据传输。 第一同步器控制器电路在具有N个第一时钟周期的第一时钟域中工作，并且第二同步器控制器电路在具有M个第二时钟周期的第二时钟域中工作，其中N / M> = 1。 反相电路将与第一时钟域相关联的第一时钟信号反相以产生反相的第一时钟信号，其用于在反相的第一时钟信号的重合边沿和与第二时钟域相关联的第二时钟信号中实现SYNC脉冲。
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公开(公告)号：US20050154840A1
公开(公告)日：2005-07-14
申请号：US10756436
申请日：2004-01-12
CPC分类号： G06F12/0822 , Y10S707/99952
摘要： Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory unit. The memory unit receives the request and determines which one of a plurality of processors other than the requesting processor has ownership of the requested cache line. The memory sends an ownership recall to that processor. In response to the ownership recall, the other processor sends the requested cache line to the requesting processor, which may send a response to the memory unit to confirm receipt of the requested cache line. The other processor may optionally send a response to the memory unit to confirm that the other processor has sent the requested cache line to the requesting processor. A copy of the data for the requested cache line may, under some circumstances, also be sent to the memory unit by the other processor as part of the response.
摘要翻译： 在共享内存多处理器计算机系统中的处理器之间传输高速缓存行所有权。 高速缓存行的所有权请求从请求处理器发送到存储器单元。 存储器单元接收该请求并确定除请求处理器之外的多个处理器中的哪一个处理器具有所请求的高速缓存行的所有权。 内存向所述处理器发送所有权回收。 响应于所有权调用，另一个处理器将请求的高速缓存行发送到请求处理器，该请求处理器可以向存储器单元发送响应以确认所请求的高速缓存行的接收。 另一个处理器可以可选地向存储器单元发送响应以确认另一个处理器已将请求的高速缓存行发送到请求处理器。 在某些情况下，所请求的高速缓存行的数据的副本也可以由其他处理器作为响应的一部分发送到存储器单元。
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公开(公告)号：US20070145163A1
公开(公告)日：2007-06-28
申请号：US11313415
申请日：2005-12-21
IPC分类号： F02M61/00
CPC分类号： F02M61/10 , F02M61/168 , F02M2200/8015
摘要： A fuel injector nozzle assembly is disclosed. The assembly may include a nozzle casing, a first tip member, and a second tip member. The first tip member may extend longitudinally within the nozzle casing and may define first and second shoulders on the first tip member. The second tip member may extend longitudinally within the nozzle casing and may be arranged in predetermined rotational alignment with the first tip member. The second tip member may define a third shoulder on the second tip member configured to interact with the first shoulder to oppose rotation of the first tip member relative the second tip member in a first direction about a longitudinal axis of the first tip member. The second tip member may further define a fourth shoulder on the second tip member configured to interact with the second shoulder to oppose rotation of the first tip member relative the second tip member in a second direction about a longitudinal axis of the first tip member.
摘要翻译： 公开了一种燃料喷射器喷嘴组件。 组件可以包括喷嘴壳体，第一末端构件和第二顶部构件。 第一尖端构件可以在喷嘴壳体内纵向延伸并且可以在第一尖端构件上限定第一和第二肩部。 第二尖端构件可以在喷嘴壳体内纵向延伸并且可以以与第一尖端构件预定的旋转对准的方式布置。 第二末端构件可以限定第二末端构件上的第三肩部，其构造成与第一肩部相互作用，以相对于第一末端构件相对于第一末端构件在第一方向围绕第一末端构件的纵向轴线旋转。 第二末端构件还可以限定第二末端构件上的第四肩部，其构造成与第二肩部相互作用以相对于第一末端构件相对于第一末端构件在第二方向上围绕第一末端构件的纵向轴线旋转。
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公开(公告)号：US12043163B2
公开(公告)日：2024-07-23
申请号：US17105774
申请日：2020-11-27
申请人： Christopher Greer , Errin Tribble
发明人： Christopher Greer , Errin Tribble
CPC分类号： B60P3/36 , H02J3/14 , H05B47/19 , H02J9/062 , H02J2310/40
摘要： A smart power center is for use in controlling DC power in mobile living quarters, such as an RV, and has switched outputs that are controlled using a mobile device, such as smartphone or tablet. The switched outputs connect DC power from a DC power source to an accessory, such as a light, fan, or motor. Some accessories, such as landing gear or slide-out rooms, require the polarity from the power source to be reversed for proper function. These are connected to reversing outputs which connect DC power from the DC power source in one orientation for one direction and a reversed orientation for the other direction. Smart override switches can be wired to the smart power center in the event the user desires to control the switched outputs without the mobile device.
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6.发明授权公开(公告)号：US07774562B2
公开(公告)日：2010-08-10
申请号：US10944524
申请日：2004-09-17
IPC分类号： G06F13/36
CPC分类号： G06F12/0813 , G06F12/0817 , G06F2212/2542
摘要： A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.
摘要翻译： 一种在多处理器系统的第一单元中操作中央高速缓存控制器（“CCC”）的方法，包括多个单元，每个单元包括全局共享存储器（“GSM”），其中第一单元被布置在第一分区中并且CCC被连接 到第一小区的多个CPU。 在一个实施例中，该方法包括响应来自CPU之一的新的事务请求，在事务表中记录事务; 确定与发送所述交易的单元对应的超时映射中的身份标识是否被设置; 并且响应于所设置的超时映射中的相应身份标识，立即向请求该事务的一个CPU返回特殊错误。
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公开(公告)号：US20210155142A1
公开(公告)日：2021-05-27
申请号：US17105774
申请日：2020-11-27
申请人： Christopher Greer , Errin Tribble
发明人： Christopher Greer , Errin Tribble
摘要： A smart power center is for use in controlling DC power in mobile living quarters, such as an RV, and has switched outputs that are controlled using a mobile device, such as smartphone or tablet. The switched outputs connect DC power from a DC power source to an accessory, such as a light, fan, or motor. Some accessories, such as landing gear or slide-out rooms, require the polarity from the power source to be reversed for proper function. These are connected to reversing outputs which connect DC power from the DC power source in one orientation for one direction and a reversed orientation for the other direction. Smart override switches can be wired to the smart power center in the event the user desires to control the switched outputs without the mobile device.
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8.发明申请公开(公告)号：US20060063501A1
公开(公告)日：2006-03-23
申请号：US10944524
申请日：2004-09-17
IPC分类号： H04B7/00
CPC分类号： G06F12/0813 , G06F12/0817 , G06F2212/2542
摘要： A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.
摘要翻译： 一种在多处理器系统的第一单元中操作中央高速缓存控制器（“CCC”）的方法，包括多个单元，每个单元包括全局共享存储器（“GSM”），其中第一单元被布置在第一分区中并且CCC被连接 到第一小区的多个CPU。 在一个实施例中，该方法包括响应来自CPU之一的新的事务请求，在事务表中记录事务; 确定与发送所述交易的单元对应的超时映射中的身份标识是否被设置; 并且响应于所设置的超时映射中的相应身份标识，立即向请求该事务的一个CPU返回特殊错误。
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